Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-10-18
2004-03-02
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S112000, C326S121000
Reexamination Certificate
active
06700412
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a MOS transistor, and more particularly to a technique for suppressing current consumption arising from band to band leak.
2. Description of the Related Art
In recent years, in the field of semiconductors, the thickness of the gate oxide film which forms a MOS transistor has reduced significantly in accordance with advancement of the refinement of the device structure. As the thickness of the gate oxide film of a MOS transistor decreases, the electric field around the drain becomes stronger, and the bend of a band on the surface of the substrate becomes greater than the band gap of silicon. As a result, a band to band tunneling phenomenon appears in an overlapping area of the gate and the drain.
If the band to band tunneling phenomenon appears, then leak current occurs between the drain and the substrate. Therefore, where the circumstances do not permit leak current arising from the band to band tunneling, a countermeasure for suppressing the band to band tunneling phenomenon is taken for the MOS transistor. Generally, as the countermeasure, the impurity concentration in the drain region in the proximity of the surface of the substrate is suppressed to moderate the intensity of the electric field.
However, even if the band to band tunneling phenomenon appears, this does not make an obstacle to functioning operation of the circuit unless holes generated then are caught by the gate oxide film and cause deterioration of a device characteristic such as the gate threshold voltage Vth. Accordingly, where only it is required that the functioning operation is guaranteed, it is not always necessary to take a countermeasure for suppressing the band to band tunneling phenomenon.
However, a semiconductor device which has a standby mode for suppressing current consumption as an operation mode has a problem in that increase of the current consumption in the standby mode arising from appearance of the band to band tunneling phenomenon gives rise to such a situation that standards for current consumption cannot be satisfied.
Also it is a problem that, if a countermeasure for suppressing the band to band tunneling phenomenon is taken, then this decreases the current driving capacity of the MOS transistor and consequently decreases the operation speed of the circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can efficiently suppress current consumption arising from a band to band tunneling phenomenon without causing a drop of the operation speed of a circuit.
In order to attain the object described above, according to an aspect of the present invention, there is provided a semiconductor device, comprising a circuit including a plurality of MOS transistors, the MOS transistors including a MOS transistor which is controlled to an off state while a predetermined potential difference is provided between a gate and a drain thereof, the MOS transistor having a band to band leak preventing countermeasure applied to the drain thereof.
With the semiconductor device, since it comprises the MOS transistor which is controlled to an off state while a predetermined potential difference is provided between a gate and a drain thereof and has a band to band leak preventing countermeasure applied to the drain thereof, current consumption arising from a band to band tunneling phenomenon can be suppressed efficiently while suppressing the drop of the operation speed of the circuit to the minimum.
According to another aspect of the present invention, there is provided a semiconductor device, comprising a plurality of circuits each including a plurality of MOS transistors, the MOS transistors including a MOS transistor which is controlled to an off state while a predetermined potential difference is provided between a gate and a drain thereof, the MOS transistor having a band to band leak preventing countermeasure applied to the drain thereof except any of the circuits for which a high operation speed is required.
With the semiconductor device, since it comprises the MOS transistor which is controlled to an off state while a predetermined potential difference is provided between a gate and a drain thereof and has a band to band leak preventing countermeasure applied to the drain thereof except any of the circuits for which a high operation speed is required, current consumption arising from a band to band tunneling phenomenon can be suppressed efficiently without sacrificing the operation speed of the circuit at all.
According to a further aspect of the present invention, there is provided a semiconductor device, comprising a circuit including a plurality of MOS transistors, the MOS transistors including a MOS transistor having a drain to which a logic level with which band to band leak can occur in a dynamic operation state is applied, the MOS transistor having a gate to which a logic level same as the logic level is applied in a static operation state.
With the semiconductor device, since it comprises the MOS transistor having a drain to which a logic level with which band to band leak can occur in a dynamic operation state is applied and has a gate to which a logic level same as the logic level is applied in a static operation state, current consumption arising from a band to band tunneling phenomenon can be suppressed efficiently without applying any countermeasure on a device and without giving rise to a drop of the operation speed of the circuit at all.
In all of the semiconductor devices above, the MOS transistor may be an n-type MOS transistor which is a component of a basic gate circuit for logical NANDing operation, and the drain thereof may be connected to an output node of the basic gate circuit.
As an alternative, the MOS transistor may be a p-type MOS transistor which is a component of a basic gate circuit for logical NORing operation, and the drain thereof may be connected to an output node of the basic gate circuit,
The MOS transistor may be a component of a basic gate circuit for logical NOT operation.
Alternatively, the MOS transistor may be a component of a static memory cell which includes a flip-flop as a principal component.
Further alternatively, the MOS transistor may be a component of a column switch for selecting a bit line pair.
The MOS transistor may drive a bit line pair in a write mode.
Otherwise, the MOS transistor may be a component of a sense amplifier which includes a flip-flop as a principal component.
Or else, the MOS transistor may be a component of a bus holder for holding the level of a data bus which is drive, for example, by a tri-state buffer.
The MOS transistor may drive a pair of data buses for transmitting a data signal composed of complementary signals in a read mode.
Further, the MOS transistor may be a component of a flip-flop.
Alternatively, the MOS transistor may be a component of a logic circuit which receives input signals at the source and the gate of the MOS transistor and performs predetermined logical operation of the input signals.
The MOS transistor may be connected at the drain thereof to a power supply or the ground.
Furthermore, the MOS transistor may be a component of a level conversion circuit for converting the signal level of an input signal.
Alternatively, the MOS transistor may be a component of a pulse generation circuit for detecting a variation of an input signal to generate a one-shot pulse.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference symbols.
REFERENCES:
patent: 5703499 (1997-12-01), Abe et al.
patent: 62-286265 (1987-12-01), None
Korean Office Action dated Jun. 28, 2003 with Japanese and partial English translations.
Sedra, et al., “Microelectronic Circuits”, Third Edition, 1989, pp. 1061-1063.
McGinn & Gibb PLLC
NEC Electronics Corporation
Tran Anh
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