Semiconductor device

Details Semiconductor device Semiconductor device

2002-04-25

2004-07-20

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S066000, C257S067000, C257S069000, C257S070000, C257S903000, C257S904000

Reexamination Certificate

active

06765272

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and is applicable to a semiconductor device having a SRAM (Static Random Access Memory).
BACKGROUND OF THE INVENTION
With reference to drawings, the basic structure of a SRAM cell that is a semiconductor memory element is described below.
As shown in a circuit diagram of
FIG. 1
, a SRAM cell is composed of a flip-flop circuit that functions as an information storage section and a pair of transmission transistors T
1
and T
2
that control the conduction between data lines (bit lines, BL
1
and BL
2
) which serve for writing and reading of the information and the flip-flop circuit. The flip-flop circuit is made of, for example, a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters, and each CMOS inverter contains a driver transistor D
1
(D
2
) and a load transistor P
1
(P
2
).
One side of source/drain regions in each transmission transistor T
1
(T
2
) is connected to drains of a load transistor P
1
(P
2
) as well as a driver transistor D
1
(D
2
), and the other side thereof is connected to a bit line BL
1
(BL
2
). Further, gates of a pair of the transmission transistors T
1
and T
2
each form a part of a word line WL and are connected with each other.
The gates of the driver transistor D
1
and the load transistor P
1
which constitute one of the CMOS inverters are connected to the drains (the storage node N
2
) of a driver transistor D
2
and a load transistor P
2
which constitute the other of the CMOS inverters. Further, the gates of the driver transistor D
2
and the load transistor P
2
which constitute the latter of the CMOS inverters are connected to the drains (the storage node N
1
) of the driver transistor D
1
and the load transistor P
1
which constitute the former of the CMOS inverters. In effect, a pair of CMOS inverters are arranged such that the input/output section of each CMOS inverters may be cross-coupled with the gate of the other CMOS inverter through one of a pair of interconnections L
1
and L
2
, which are called the local interconnections.
Further, a reference voltage (V
ss
, for example, GND) is applied to the source region of each one of the driver transistors D
1
and D
2
, and a supply voltage (V
cc
) is applied to the source region of each one of the load transistors P
1
and P
2
.
FIG. 2
is a diagram showing the ordinal layout of a conventional SRAM cell which corresponds to the circuit diagram of FIG.
1
.
In the drawing, AR indicates an active region, in which a dopant diffusion region to constitute one of the transistors is formed. Further, an area shown by a chain line in the drawing is a region for one memory cell, and a number of memory cells are arranged side by side along the direction of the length of the word line to form an array, and arrays of memory cells are regularly disposed in the direction perpendicular to this direction of the length.
Referential numerals
117
and
118
indicate contact sections for the bit line BL
1
and the bit line BL
2
, respectively;
121
and
122
, contact sections for the supply voltage line;
123
and
124
, contact sections for the reference voltage line (ground line). Contact sections
116
,
111
and
113
are connected to one another through a local interconnection L
1
which is not shown in the drawing, while contact sections
115
,
112
and
114
are connected to one another through a local interconnection L
2
which is neither shown in the drawing. The transmission transistor T
1
is composed of a portion of the word line WL lying between the contact sections
113
and
117
and diffusion regions lying on both side thereof, and the transmission transistor T
2
, a portion of the word line WL lying between the contact sections
114
and
118
and diffusion regions lying on both sides thereof. The driver transistor D
1
is composed of a portion of an interconnection
131
lying between the contact sections
113
and
123
and diffusion regions lying on both sides thereof, and the driver transistor D
2
, a portion of an interconnection
132
lying between the contact sections
114
and
124
and diffusion regions lying on both sides thereof. The load transistor P
1
is composed of a portion of the interconnection
131
lying between the contact sections
111
and
121
and diffusion regions lying on both sides thereof, and the load transistor P
2
, a portion of the interconnection
132
lying between the contact sections
112
and
122
and diffusion regions lying on both sides thereof.
The SRAM cell described above has excellent element characteristics such as the high noise tolerance and the small stand-by power. Further, for the SRAM cell of this sort, in view of element characteristics, selection of the materials and layout are carefully made so as not to lose symmetry of the element structure (in other words, to prevent imbalance from occurring) within the limits of possibility,.
However, such a SRAM cell has a problem that a cell area tends to become considerably large, due to requirements to have 6 transistors in one memory cell and isolate p-type MOSFETs from n-type MOSFETs within one and the same cell as well as the need of numerous interconnections.
Accordingly, for a semiconductor memory device having a SRAM of this sort, an improvement in the integration level is one of the prime issues. Even if a reduction made in one memory cell is small, the degree of integration can be greatly raised, as a whole, in a semiconductor memory device of high integration. It is, therefore, important to make the area of the memory cell as small as possible. For that purpose, accompanying the recent progress in manufacturing technology, great efforts have been made to achieve, in addition to miniaturization of fabrication size and improvement of layout design, further reduction of the spacing of the interconnections as well as the distance between the interconnection and the contact section.
However, when the distance between the gate electrode of the transistor and the contact section disposed on the dopant diffusion region becomes excessively small, a problem of the leakage arises. This phenomenon occurs notably in the p-type MOSFETs which constitute the load transistors P
1
and P
2
, and the standby current in the memory cell may increase, owing to the leakage generation. Such a phenomenon causes a serious problem, particularly in the Low Power type SRAM.
The generation of the leakage becomes marked, if the contact section for the source/drain region is in contact with the LDD (Lightly Doped Drain) region. One of the reasons for that is considered to be the movement of the dopants in the LDD region, being drawn to the side of the contact section. Since the dopant concentration in the LDD region is lower than that in the source/drain region which is a dopant diffusion layer of high concentration, the LDD region is readily affected by the dopants drawn thereto, with its dopant concentration being easily changed, and this may lead to a failure to form the junction as prescribed.
Further, the reason why the leakage is notable in the p-type MOSFETs is thought to lie in a fact that boron used as p-type dopants is liable to be drawn heavily to the contact section. Especially when a titanium-based metal film is employed as a barrier film to constitute the contact section, the leakage becomes marked. The explanation is considered to be made as follows. Due to the effects of a heat treatment conducted in fabrication, a titanium silicide layer is formed on a contact interface between the titanium-based metal film and the silicon substrate, and it is chiefly this titanium silicide layer that draws boron thereat.
Meanwhile, for the purpose of lowering the sheet resistance and the contact resistance caused by the contact section, a refractory metal silicide layer may be set over dopant diffusion regions which constitute source/drain regions. In Japanese Patent Application Laid-open No. 177067/1994, there is described a problem that, in such a structure, especially in a structure wherein a titanium silicide layer is formed

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