Semiconductor device

Details Semiconductor device Semiconductor device

1998-12-14

2004-05-18

Donghee, Kang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S370000, C257S371000, C257S375000, C257S392000, C438S199000, C438S217000, C438S218000, C438S284000, C438S286000

Reexamination Certificate

active

06737709

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, more specifically a complementary metal oxide semiconductor (CMOS) device having a p-channel MOS (hereafter called a PMOS) field effect transistor (FET) using holes as carriers and an n-channel MOS (hereafter called an NMOS) FET using electrons as carriers on the same chip.
2. Description of the Related Art
At the present time, most CMOS integrated circuits use a so-called two-layer “polyclde” structure of a metal sillicide layer and polycrystalline silicon layer for their gate electrodes so as to decrease the resistance of their gate electrodes.
In CMOS's having an NMOSFET and PMOSFET on the same substrate, it is generally known to use a so-called “dual gate” structure for the gate electrodes from the viewpoints of suppressing the, short channel effect, controlling the threshold voltage, etc.
A CMOS having a dual gate structure is configured for example as shown in FIG.
1
.
As shown in
FIG. 1
, element formation regions
104
and
105
at which the PMOS and NMOS are to be formed are enclosed by an element isolation region
103
. A polycrystalline silicon layer
106
is formed on these element formation regions
104
and
105
over the element isolation region
103
.
A p
+
-type impurity is doped in the region of the polycrystalline silicon interconnection layer
106
over the element formation region
104
for forming the PMOS, while an n
+
-type impurity is doped in the region of the polycrystalline silicon interconnection layer
106
over the element formation region
105
for forming the NMOS. These doped regions are thereby made conductive and form gate electrodes
101
and
102
. Note that the gate electrodes
101
and
102
are electrically connected with each other by a metal sillicide layer formed on the polycrystalline silicon interconnection layer
106
in a later step.
In the CMOS illustrated in
FIG. 1
, the impurities doped in the gate electrodes
101
and
102
tend to diffuse into the region
106
a
of the polycrystalline silicon layer
106
not doped with impurities.
If impurities diffuse into the region
106
a
, the impurities doped in the gate electrodes
101
and
102
will be depleted, the density of the impurities at the gate electrodes will fall, the change in the threshold voltage V
th
, and a fall in the current I
DS
between the drain and source due to depletion of the gate electrodes will be caused.
To prevent a fall in the current I
ds
between the drain and source, for example, a CMOS having the structure shown in
FIG. 2
has been proposed.
In the CMOS shown in
FIG. 2
, the gate electrode
101
doped with the p
+
-type impurity and the gate electrode
102
doped with the n
+
-type impurity are formed over the element formation regions
104
and
105
and extending off over the element isolation region
103
.
That is, when forming the gate electrodes
101
and
102
doping impurities, the impurities are doped in the polycrystalline silicon layer
106
so as to extend off by lengths L
diff
from the element formation regions
104
and
105
.
Accordingly, the extended regions
101
a
and
102
a
become sources of stored impurities.
Note that the width 2×L
ovlp
of the region
106
a
of the polycrystalline silicon interconnection layer
106
which is not doped with an impurity is a margin of saf ty s t in view of possible mask misalignment at the time of ion implantation of impurities into the polycrystalline silicon interconnection layer
106
.
The length L
diff
is the length required to prevent a drop in the density of impurities in the gate electrodes
101
and
102
.
Accordingly, the drop of the density of impurities in the gate electrodes
101
and
102
can be considerably suppressed and a drop of the current I
DS
between the drain and source can be prevented.
The problem is that, in the CMOS shown in
FIG. 2
, the distance L
p
between the element formation regions
104
and
105
for forming the PMOS and NMOS becomes 2×(L
diff
+L
ovlp
).
To make the extended regions suitably function as sources of stored impurities, the certain extent of the length L
diff
is needed, for example, if L
g
is 0.2 &mgr;m, L
diff
must be 0.3 &mgr;m.
Thus, it is difficult to shorten the distance L
p
between the PMOS and NMOS to further reduce the chip area.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a CMOS device having a dual gate structure suppressing lateral diffusion of the impurities doped in the n-type and p-type gate electrodes, further shortening the distance between the PMOS and NMOS, and enabling further reduction of the chip size.
According to the present invention, there is provided a semiconductor device comprising a first element formation region in which a device of a first conductivity type is formed; a second element formation region separated from the first element formation region by an element isolation region and in which a device of a second conductivity type different from the first conductivity type is formed; a first gate electrode provided on the first element formation region and containing an impurity of the first conductivity type; a second gate electrode provided on the second element formation region facing the first gate electrode and containing an impurity of the second conductivity type; a first impurity storage region containing the first conductivity type impurity, having one end connected to an end of the first gate electrode, and arranged in a direction different from the direction of arrangement of the first and second gate electrodes; and a second impurity storage region containing the second conductivity type impurity, having one end connected to an end of the second gate electrode, having the other end electrically connected to the other end of the first impurity storage region, and arranged in a direction different from the direction of arrangement of the first and second gate electrodes.
Preferably, the first and second impurity storage regions are physically connected to each other by a semiconductor layer.
More preferably, the semiconductor layer is formed by polycrystalline silicon and the first and second gate electrodes and first and second impurity storage regions are formed by selectively implanting impurities to the polycrystalline silicon layer.
Alternatively, more preferably the width of the semiconductor layer physically connecting the first and second impurity storage regions is a value allowing mask misalignment when forming the first and second gate electrodes and first and second impurity storage regions.
Alternatively, preferably the other ends of the first and second impurity storage regions are electrically connected to each other through a conductive layer.
Alternatively, preferably the first and second impurity storage regions are arranged in a direction perpendicular to the direction of arrangement of the first and second gate electrodes.
Alternatively, preferably the first and second gate electrodes and the first and second impurity storage regions are formed in the same conductive semiconductor layer.
Alternatively, preferably a semiconductor device as set forth in claim
1
, wherein the element isolation region is buried in a trench formed a boundary between the first and second conductive type of element formation regions in a semiconductor substrate.
Alternatively, preferably the element isolation region isolates first and second element formation regions comprised of semiconductor layers formed on an insulation layer.
More preferably, the element isolation region is buried in a trench formed in the semiconductor layers.
Alternatively, preferably the widths of the first and second impurity storage regions are equal to the gate length of the first and second gate electrodes and the lengths of the first and second impurity storage regions are longer than the gate length.
In the semiconductor device according to the present invention, by providing the first impurity storage region connected to the first gate e

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