Semiconductor device

Details Semiconductor device Semiconductor device

2002-08-05

2004-05-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189090, C365S211000

Reexamination Certificate

active

06731558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an arrangement of a self-refresh control circuit for internally and periodically rewriting and refreshing the stored data of a memory cell. More specifically, the present invention relates to an arrangement of refresh request generating circuitry for issuing a refresh request that provides a timing for performing the refresh in a self-refresh mode.
2. Description of the Background Art
FIG. 15
is a schematic diagram showing an arrangement of the main portion of a conventional semiconductor memory device. In
FIG. 15
, a semiconductor memory device includes a memory cell array
900
having a plurality of memory cells arranged in rows and columns, a row-related circuit
902
for selecting a row of memory cell array
900
, when activated, according to a row address signal supplied, a column-related circuit
904
for selecting a column of memory cell array
900
, when activated, according to a column address signal supplied, a command decoder
906
for decoding a command CMD externally supplied to generate an operating mode instruction signal instructing an operation mode designated by this command, a row-related control circuit
908
for activating row-related circuit
902
according to a row select instruction signal from command decoder
906
, a refresh control circuit
910
rendered active in response to a self-refresh instruction from command decoder
906
for performing an operation necessary for the refresh, and a refresh timer
912
rendered active in response to a self-refresh mode instruction signal SELF from refresh control circuit
910
for issuing and supplying to refresh control circuit
910
a refresh request PHY in prescribed periods.
Command CMD normally designates an operating mode by a combination of the logic levels of prescribed external signals (control signals and specific address signal bits), for instance, at a rising edge of a clock signal. Command CMD may be supplied with a single signal, instead.
Refresh control circuit
910
starts refresh timer
912
when the self-refresh instruction signal is supplied from command decoder
900
. Refresh timer
912
is started upon the activation of self-refresh mode instruction signal SELF and issues refresh request PHY in prescribed periods.
When refresh request PHY is issued, refresh control circuit
910
generates and supplies to row-related control circuit
908
a refresh activating signal RFACT. When refresh activating signal RFACT is activated, row-related control circuit
908
activates row-related circuit
902
to select a row of memory cell array
900
. During the row selection of memory cell array
900
in the refresh mode, a refresh address from a refresh address counter, not shown, is utilized for the refresh row designation.
Row-related circuit
902
includes a circuit portion related to the row selection such as a row address decoder and a word line drive circuit, while column-related circuit
904
includes a circuit related to column selection such as a column decoder.
A memory cell arranged in memory cell array
900
is a DRAM cell (Dynamic Random Access Memory Cell) for storing information in a capacitor. Thus, in order to prevent the stored data of the memory cell from being dissipated due to a leakage current of the capacitor, the refresh operation is performed in prescribed periods according to refresh request PHY from refresh timer
912
, to hold the stored data.
Normally, a ring oscillator is used in refresh timer
912
. When activated, the ring oscillator is equivalently formed of an odd-number of stages of CMOS inverters. The operating speed of a CMOS inverter does not change so much within the operating temperature range. Therefore, by setting the refresh period according to the worst data holding time period of a memory cell, the stored data of the memory cell of memory cell array
900
can be held with certainty.
The CMOS inverter is formed by a P-channel MOS transistor and an N-channel MOS transistor, and the operating speed of the CMOS inverter may decrease a little due to the influence of hot carriers but would not change so much within the operating temperature range.
On the other hand, charges corresponding to the stored data are accumulated at a storage node of a capacitor in a memory cell. The storage node is coupled to an impurity region formed on a surface of a semiconductor substrate region. The impurity region is coupled to a source/drain region of an access transistor of the memory cell.
The impurity region of the storage node and the semiconductor substrate region are of different conductivity types so that a PN junction is formed between the both. When the leakage current of the PN junction becomes great, the charges accumulated in the storage node flow out and the stored data is lost. The leakage current of the PN junction has a positive temperature dependency and increases with the rise in the temperature. Since the leakage current has a temperature dependency, the data holding period of the memory cell also has a negative temperature dependency. Consequently, in order to ensure that the store data of the memory cell is held, there is a need to change the cycle of self-refresh according to the operating temperature. Thus, in the self-refresh mode, there is a need to shorten the refresh intervals as the operating temperature rises when performing the refresh operation.
In this case, in the case when the refresh cycle is set fixedly, according to the operating temperature, to the worst (shortest) refresh cycle corresponding to a high operating temperature, the refresh cycle would become unnecessarily short under a normal operating temperature region around a room temperature, and the current consumed in the self-refresh becomes great in amount. In particular, the self-refresh is performed in a standby state during which data is merely held, so that there arises a problem of increased standby current. Particularly, when the power supply is a battery as in the case of a portable equipment and the like, there is a need to reduce the consumed current in the self-refresh that is performed in a data hold mode such as a sleep mode, in order to lengthen the battery life.
In order to compensate for such temperature dependency of the refresh cycle, as shown in
FIG. 16
, a temperature sensor
925
may possibly be provided outside a semiconductor memory device
920
, while internally disposing a temperature compensation circuit
930
for compensating for the cycle of refresh timer
912
according to a detected temperature of temperature sensor
925
. Temperature sensor
925
is formed by a thermistor, for example, and according to the detected current or temperature of the thermistor, temperature compensation circuit
930
disposed within semiconductor memory device
920
controls the operating current of the ring oscillator forming refresh timer
912
.
When such temperature sensor
925
is provided outside semiconductor memory device
920
, however, temperature sensor
925
would be formed by a thermistor or a thermocouple, for instance, which occupies a large area, so that the area occupied by the entire system would increase.
In addition, in order to supply an output signal from temperature sensor
925
to temperature compensation circuit
930
provided inside semiconductor memory device
920
, an extra pin terminal would be required for temperature compensation, which disadvantageously increases the assembling area of semiconductor memory device
920
.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor memory device capable of performing temperature compensation of a self-refresh cycle with certainty and with small occupying area.
A semiconductor memory device according to the present invention includes a reference voltage generating circuit for generating a reference voltage having a temperature dependency, and a refresh request generating circuit having its operating speed defined by the reference voltage

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