Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-07-26
2004-09-07
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S081000, C326S083000, C326S119000, C326S068000, C327S390000, C345S204000, C345S094000, C345S100000
Reexamination Certificate
active
06788108
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inverter, buffer, and level shifter, and to a semiconductor device using them. Note that the term display device used within this specification includes a liquid crystal display device which employ liquid crystal elements in pixels, and a light emitting device which employ light emitting elements such as electro-luminescence (EL) elements. The term semiconductor device indicates circuits that perform processing for inputting video signals into pixels disposed in the display device and displaying images. Pulse output circuits such as shift registers, inverters, buffers, and level shifters, and amplification circuits such as amplifiers are included in the category of semiconductor devices.
2. Description of the Related Art
In recent years, display devices manufactured by forming semiconductor thin films on an insulator such as a glass substrate, in particular, active matrix display devices such as LCDs (liquid crystal displays) using thin film transistors (hereinafter referred to as TFTs), are being utilized in many manufactured products, and are spreading. The active matrix display devices using TFTs have from several hundred thousands to several million pixels arranged in a matrix shape, and display of images is performed by controlling the electric charge of each pixel with TFTs disposed in the respective pixels.
In addition, techniques related to polysilicon TFTs for TFTs have been developed recently, and a driver circuit using TFTs is formed in a peripheral region of a pixel portion on a substrate simultaneously with pixel TFTs structuring pixels. The techniques contribute greatly to making a device small size and to reducing electric power consumption, and accordingly, a display device has come to be indispensable for a portion such as a display portion of a mobile information terminal, which has remarkably been applied to the extensive fields in recent years.
In general, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined are used as a circuit for structuring semiconductor devices. A CMOS inverter is shown in
FIG. 11A
as one example of the CMOS circuit. A p-channel TFT
1101
and an n-channel TFT
1102
are combined, and an output signal is obtained by inverting the polarity of an input signal (see FIG.
11
B).
Now, as shown in
FIG. 11C
, there is a state in which a certain load (Load) is attached to the later stage of the CMOS inverter. If the load is excessive with respect to the size of the TFTs structuring the CMOS inverter at this point and a pulse is input from an input (In), there will be a case in which an output pulse, namely an output (Out i) of an inverter (Inv
1
) in
FIG. 11C
, is greatly dulled in both rise and fall of the pulse, compared to the waveform of the input signal, as shown in FIG.
11
E. This is because the CMOS itself inverter does not have the capability of supplying a sufficient amount of electric charge for driving the load.
There normally is lot of weight given to low electric power consumption with semiconductor devices, and logical circuits are structured using relatively small size TFTs. On the other hand, display regions are becoming larger in size, and in addition, the number of pixels is increasing. The load due to the pixels is therefore large. As stated above, pulses are not output normally if a large load is present in the later stage of an inverter with a small driving capability.
A buffer is normally formed between a driver circuit portion and a pixel portion. Typically, a plurality of inverter stages are disposed in series as shown in
FIG. 11D
, and driving of the final load can be performed without problem by driving the inverters that are gradually increased in size. Compared to the structure of
FIG. 11C
, the waveform of an output (Out ii) of a buffer in the final stage (Inv
4
) is not greatly dulled and thus is output as a normal pulse, and the load in the later stage can be driven.
Display devices have come to be employed in the display portion of many types of electronic devices in recent years, and there is steady expansion in the number of fields in which display devices are used. Display devices are recently being actively employed even in relatively low cost electronic equipment, and therefore further cost reductions are desirable.
A multiple-layer structure is formed for a display device by repeatedly performing processes of film formation, exposure to light using a photomask, and etching. The extreme complexity of the processes therefore invites an increase in manufacturing costs. In addition, in the case in which the driver circuit and the pixel portion are formed integrally on the substrate as discussed above, some defects become a problem which affects the entire manufactured product, and has a large influence on yield.
A method in which the number of processes is reduced as much as possible, and manufacturing can be performed simply in a short period of time can be given as one method of achieving the cost reduction. A display device is manufactured with a structure that uses TFTs with a single polarity type, n-channel TFTs or p-channel TFTs, instead of a CMOS structure for the driver circuit. Processes for adding an impurity which imparts a conductivity to a semiconductor layer can thus be simply cut in half, and in addition, the number of photomasks can be reduced. This is extremely effective from the vie point of cost-related merits.
A conventionally known single polarity type circuit is explained here.
FIG. 12A
shows an example in which an inverter is structured by two n-channel TFTs. The inverter is a two input type inverter with signals input to gate electrodes of TFTs
1201
and
1202
. An inverted signal of one input is used as the other input.
Operation of the inverter shown in
FIG. 12A
is explained simply here. Note that the terms “gate electrode, input terminal, and output terminal”, and the terms “gate electrode, source region, and drain region” are used separately in this specification for the names of the three electrodes of the TFT in explaining the circuit structure and operation. This is because, although there are many cases in which the voltage between the gate and the source is considered in explaining TFT operation, it is difficult to clearly differentiate the source region and the drain region of the TFT based upon the structure of the TFT and the use of unified names may, instead of being helpful, lead to confusion developing. The terms input terminal and output terminal are used in explaining the input and output of signals. The input terminal or the output terminal is referred to as the source region, and the other is referred to as the drain region, in explaining the relationship of the electric potential between the electrodes of the TFT.
First, operation of the two input inverter of
FIG. 12A
is explained. When H level is input to a first input (In) and L level is input to a second input (Inb), the TFT
1201
turns off and the TFT
1202
turns on. L level therefore appears in an output (Out) and the electric potential of the output becomes VSS. On the other hand, when L level is input to the first input (In), and H level is input to the second input (Inb), the TFT
1201
turns on and the TFT
1202
turns off. H level therefore appears in the output (Out) to pulled up to the VDD side.
At this point, the electric potential is considered when the output (Out) become the H level.
The L level is input to the gate electrode of the TFT
1202
when the H level is input to the gate electrode of the TFT
1201
in FIG.
12
A. The TFT
1201
is therefore on, and the TFT
1202
is therefore off. Accordingly, the electric potential of the output (Out) begins to rise, and the voltage between the gate and the source of the TFT
1201
becomes equal to the threshold value VthN when the electric potential of the output (Out) becomes (VDD−VthN). That is, the TFT
1201
turns off at this instant, and therefore the electric potential of the output (Out) cannot rise any further.
A cir
Miyake Hiroyuki
Shionoiri Yutaka
Fish & Richardson P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Tan Vibol
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