Semiconductor device

Details Semiconductor device Semiconductor device

2003-10-03

2004-09-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S230060

Reexamination Certificate

active

06798686

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor storage devices such as a dynamic memory (DRAM) and a nonvolatile ferroelectric memory.
2. Description of the Related Art
These days, a semiconductor memory is broadly been utilized as a storage device in electronic apparatuses such as, large-sized computers, personal computers, household electric products, and mobile phones. Examples of the semiconductor memory appearing on the market include a volatile dynamic RAM (DRAM), static RAM (SRAM), nonvolatile mask ROM (MROM), FlashE
2
PROM, and the like. Although particularly the DRAM is a volatile memory, it is superior in terms of low cost and high speed, and occupies a major part of the market at present. On the other hand, a nonvolatile ferroelectric memory using a ferroelectric capacitor has been developed by respective makers, as it has a nonvolatile property, is many rewritable up to 10
12
times, and has a read/write time as short as that of a DRAM, and the like.
FIG. 28A
shows a circuit diagram of a conventional DRAM, and
FIG. 28B
shows a signal chart of an operation of the DRAM. As shown in
FIG. 28A
, one cell transistor CT
0
is connected in series with one paraelectric capacitor CC
0
, one end (capacitor CC
0
side) is connected to a plate line (PL), and the other end (cell transistor CT
0
side) is connected to a bit line BL. Assuming that an amplitude voltage of the bit line is Vaa, the plate line is usually fixed at 1/2Vaa.
As a problem of the conventional DRAMs, the voltage of a word line WL for selecting a cell needs to be set to a boosted high voltage Vpp, the voltage applied to a memory cell transistor increases as a result, and size reduction of the memory cell transistor (size reduction of a gate oxide film thickness Tox, channel length L, or the like) cannot be realized.
As shown in
FIG. 28B
, during the operation, the voltage of the word line WL is raised to the voltage Vpp, and data is read into the bit line BL from a cell node CN
0
of the DRAM cell. Thereafter, a sense amplifier is operated. When the data is “1” data, the voltage of the bit line BL is amplified to Vaa. When the data is “0” data, the voltage of the bit line BL is amplified to Vss. The result is rewritten into the cell node CN
0
. Therefore, when the “1” data, that is, Vaa is rewritten into the cell node CN
0
, a threshold voltage of the cell transistor is set to Vtcell, then Vpp>Vaa+Vtcell, and a high voltage, that is, the boosted voltage Vpp is required. In order to lower the voltage Vpp, the voltage Vaa and/or Vtcell may be reduced. However, when the voltage Vaa is lowered, a charge accumulated in the cell decreases, and deterioration of a data holding property and deterioration of a low voltage operation are caused. On the other hand, when Vtcell is lowered, the accumulated charge of the cell leaks to the bit line via the cell transistor, and the data holding property is deteriorated. Therefore, it is difficult to lower the voltage Vpp. For a conventional DRAM, the “0” data as well as the “1” data are rewritten. With the “0” data, the bit line voltage is Vss. The boosted voltage Vpp at maximum is applied between gate and source of the cell transistor, that is, between word line and cell node, as shown by the waveform WL−CN
0
on the signal chart.
As described above, in a conventional DRAM, in order to maintain the holding property of the data to be satisfactory, Vtcell cannot be lowered, the high voltage, that is, the boosted voltage Vpp needs to be applied to the cell transistor as a result, and this inhibits a size reduction of the cell transistor. Therefore, a problem occurs that the memory cell size cannot be reduced, and a chip size cannot be reduced. When the size of the cell transistor is forced to be reduced, insulating film collapse, deterioration of an operation property due to a Hot Carrier, and Ioff increase by a short channel effect are generated. Therefore, with a design rule of the same development generation, as compared with a logic LSI, the gate oxide film thickness Tox and channel length L of the cell transistor of the DRAM are large by 30 to 50 percentages in actual circumstances. In addition to the problem that the chip size cannot be small, the problem of slow operation speed occurs in a DRAM-Logic mixed chip in which a logic section is constituted of a transistor having the same size as a cell transistor of the DRAM. To solve the problem, in a conventional technique, for a high-performance DRAM-Logic mixed chip, a transistor having a large Tox and L is used in the DRAM cell transistor, core section requiring the boosted voltage, and I/O section. On the other hand, a transistor having a small Tox and L is used in a DRAM peripheral circuit and the logic section. However, in this case, since two types of transistors are formed, the problem of process cost increase arises.
On the other hand, a method of driving a potential of the plate line PL and lowering Vpp with respect to the conventional DRAM is disclosed in the following.:
1) K. Fujishima et al. “A storage-node-boosted RAM with word line delay compensation” International Solid-State Circuits Conference Digest Technical Paper, pp. 66-67, 1982;
2) M Aoki et al. “A 1.5 DRAM for battery-based application” IEEE Journal of Solid-State Circuits, vol. 24, No. 5, pp. 1206-1212, October 1989; and
3) T. Yamauchi et al. “High-performance embedded SOI DRAM architecture for a low-power supply” IEEE Journal of Solid-State Circuit, vol. 35, No. 8, pp. 1169-1178, August 2000.
A circuit constitution of the DRAM of this system and a signal chart of the operation are shown in
FIGS. 29A
,
29
B. In the DRAM of this system, the plate line potential PL is amplified between Vss and Vaa, the bit line potential is amplified to Vaa (for “1” data) or Vss (for “0” data), thereafter the plate line potential PL is lowered to Vss, and “1” data of Vpp Vtcell is written into the cell node CN
0
. Subsequently, the word line potential is lowered to some degree, the “1” data is prevented from leaking, the plate line potential PL is lowered to Vaa, and the “0” data of Vss is written into the cell node CN
0
in this system.
When the plate line potential PL is driven in this manner, as a result, a potential difference Vsig (
1
:
0
) of the “1” data and “0” data is Vsig(
1
:
0
)=Vpp−Vtcell+Vaa. The data is held to be satisfactory as compared with Vsig(
1
:
0
)=Vaa of the DRAM of a conventional plate line potential PL fixed system. According to this system, a doubled signal can be written similarly as use in the ferroelectric memory. However, on the condition of Vpp<Vaa+Vtcell, Vsig(
1
:
0
)=Vpp−Vtcell+Vaa<2Vaa. For example, as shown in
FIG. 29B
, on Vpp=Vaa, Vsig(
1
:
0
)=2Vaa−Vtcell. Consequently, similarly as in the DRAM of
FIGS. 28A
,
28
B, the data is deteriorated because of a drop in the threshold value of the transistor. Moreover, in order to drive the plate line potential PL, the plate line needs to be separated for each memory cell, and the cell size increases. Another problem is that the driving of the plate line takes much time, which delays the operation.
This problem occurs not only in a DRAM but also in a ferroelectric memory. Examples of a conventional ferroelectric memory include a memory whose plate line potential PL is fixed (the paraelectric capacitor of
FIG. 28A
is replaced with a ferroelectric capacitor), and a memory whose plate line potential PL is driven (the paraelectric capacitor of
FIG. 29A
is replaced with a ferroelectric capacitor), and the problem is generated similarly as described above. Moreover, for a ferroelectric memory, the inventor of the present application has proposed a new nonvolatile ferroelectric memory in U.S. Pat. No. 5,903,492 characterized by three factors: (1) use of a small memory cell with a 4F2 size; (2) use of an easily manufacturable flat transistor; and (3) use of a general-purpose random access function. In the ferroelectric memory disclosed in the U

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