Semiconductor device

Details Semiconductor device Semiconductor device

2002-03-27

2003-10-21

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

C257S622000, C257S626000, C257S797000

Reexamination Certificate

active

06635952

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-090909 filed on Mar. 27, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor device using an SOI substrate, and more particularly to a semiconductor device suited to a high-speed logic LSI.
Over the recent years, there has been attempted a scheme of attaining both of a speed-up of LSI and a reduction in consumption of the electric power by utilizing an SOI (Silicon On Insulator) substrate.
FIG. 12
is a device sectional view showing one example of a semiconductor device using the SOI substrate described above.
FIG. 12
illustrates how a MOSFET is manufactured by use of the SOI substrate including a buried oxide layer (BOX layer)
2
and an active silicon layer (SOI layer)
3
provided on a silicon substrate (support substrate)
1
.
This MOSFET is configured such that a gate insulating film
5
is provided in a region where a channel is to be formed on the surface of a region surrounded by an element isolation layer
4
in the active silicon layer
3
, a gate electrode
6
having side walls
7
and a metal silicide layer
8
on the surface thereon is provided on the gate insulating film
5
, and high-concentration source/drain regions
10
and a low-concentration ion implantation regions
9
taking an LDD structure are provided sideways of the gate electrode in the active silicon layer
3
. A metal silicide layer
11
is provided on the surface of the high-concentration source/drain regions
10
. This metal silicide layer
11
is connected to a tungsten film
13
filled into a contact openings formed in an inter-layer insulating layer
12
and led out as a source/drain electrode
14
on the inter-layer insulating layer
12
.
The thus configured MOSFET is capable of attaining a remarkable reduction in parasitic capacitance of the source/drain region
10
, and therefore a speed-up of the device can be expected.
Besides, this MOSFET basically does not have much difference from the MOSFET using a normal bulk wafer except that the substrate is the SOI substrate. Accordingly, especially in the case of a partial depletion type MOSFET, the manufacturing process is almost the same except for having different conditions such as an ion implantation and so on.
As a result, the SOI semiconductor device can be manufactured on a trial basis simply by using the SOI substrate as the substrate, wherein the manufacturing process using the bulk substrate is applied as it is. The SOI semiconductor device therefore has an advantage that the performance can be enhanced without any rise in load on the development.
Furthermore, with a demand for speeding up the system with respect to the semiconductor device utilizing the SOI technology, there has increasingly been a request for providing a memory device such as a DRAM etc and a logic device on the same chip. Under such circumstances, there arises a necessity of mounting the high-speed logical circuit and the memory device together on the SOI substrate. A problem of deteriorating a retention, however, arises, wherein the DRAM on the SOI substrate is easy to cause a leak of electric charges and required to be frequently refreshed.
For avoiding this problem, a scheme of adopting an SOI substrate partially having the bulk structure is proposed.
FIG. 13
is a sectional perspective view showing this structure.
This SOI substrate has such a basic structure that an buried oxide layer
22
and an upper silicon layer
23
are stacked on a silicon substrate
21
, wherein the upper silicon layer
23
and the buried oxide layer
22
are partially opened, and these openings are filled with selective epitaxial growth layers
24
to connect with the substrate
21
, thus providing the partial bulk structure.
In the case of providing the DRAM in this region, the problem of retention can be avoided.
When using the SOI substrate, however, there is the following problem with respect to forming an identifying mark.
When manufacturing the LSI on the trial basis, a wafer used is marked in its specified position with a number etc for identifying the wafer. Hence, for example, the substrate is irradiated with laser beams so that the substrate is formed with crater-like cavities having a diameter on the order of 50 through 70 &mgr;m and a depth on the order of 2 through 4 &mgr;m, and numerals and characters are expressed by utilizing an aggregation of these cavities.
FIGS. 14A through 14C
show how numbering is effected on the SOI substrate by executing the same process.
FIG. 14A
is a view showing these cavities as viewed from above.
FIG. 14B
is a view showing the same cavities as viewed obliquely from above.
FIG. 14C
is a view showing the same cavities as viewed in section taken along the line B—B′ in FIG.
14
B.
When the numbering is thus effected on the SOI substrate, as can be seen from the enlarged view in
FIG. 14B
, minute dusts are scattered to the periphery of the depletion. A cause of these dusts can be presumed as follows from the sectional view in FIG.
14
C. Namely, the active silicon layer and the buried oxide layer on the SOI substrate are as thin as 0.1 through 0.2 &mgr;m and 0.2 through 0.4 &mgr;m, respectively. Therefore, when heated by the laser beams to form the cavities of 2 through 4 &mgr;m, the active silicon layer and the buried oxide layer are flicked away in fragments, and these fragments are, it is presumed, scattered to and accumulated along the peripheries of the cavities. These silicon fragments turn out to be dusts that also cause a decline of yield of the transistor.
Further, because of the SOI substrate having the buried oxide layer, a configuration and a color of the mark sued for a mask alignment are different from those in the bulk wafer, and what can be detected on the bulk wafer but can not detected on the SOI substrate. Therefore, even if manufactured in the same process as the bulk wafer, a mark detecting condition only for the SOI substrate is required as the case may be. Further, when obtaining QC (Quality Control) data during the process, a QC data measurement recipe only for the SOI substrate must be created due to the fact that the same measurement as the bulk wafer can not be conducted because of the buried oxide layer existing therein though the process is the same as the bulk wafer.
Moreover, in the case of taking the partial bulk structure described above, the following problem arises if the memory devices are provided in a plurality of regions.
FIGS. 15A through 15C
illustrate this problem and are step-by-step sectional views showing manufacturing steps in the case of providing the plurality of regions formed with the memory devices. Referring to
FIGS. 15A through 15C
, the same components as those in
FIG. 13
are marked with the same reference numerals.
An SOI substrate including an buried oxide layer
22
and an upper silicon layer
23
stacked in sequence on a silicon substrate
21
, is prepared (FIG.
15
A). An insulating layer
20
such as a silicon oxide layer and a unillustrated resist layer are provided thereon, and patterning is effected thereon, thus providing an etching mask. Etching is executed by use of this etching mask, thereby removing the buried oxide layer
22
and the upper silicon layer
23
in the memory device forming region. Openings are thus formed, and subsequently, after removing the resist layer, epitaxial growth layers
25
,
26
are provided by effecting the selective epitaxial growth in these openings. As in this example, however, if the opening regions have different areal sizes, a speed of the epitaxial growth differs depending on the openings, with the result that a level difference in filling configuration between the openings occurs (FIG.
15
B). Even in a state where the insulating layer
24
is finally removed, the level difference between the epitaxial growth layers
25
and
26
is left (FIG.
15
C).
This level di

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