Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-08-19
2003-12-09
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S748000, C257S750000, C257S774000, C257S358000
Reexamination Certificate
active
06661095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a high-resistance element, and more specifically, to a semiconductor device in which a high-resistance element is used in an analog circuit.
2. Description of the Background Art
Conventionally, a high-resistance element has been used in an analog circuit of many LSI (Large Scale Integration) devices such as memory LSI devices. In the analog circuit, the characteristics of the high-resistance element significantly effect the operation of the circuit, often determining the characteristics of the LSI device itself.
As a representative example, in a reference potential Vref generating circuit, fluctuation of the resistance value of a high-resistance element may even changes the reference potential generated by the circuit.
In the following, portions of a conventional semiconductor device where a high-resistance element is used will be described referring to top views or cross-sectional views of
FIGS. 16
to
18
.
As shown in
FIGS. 16
to
18
, a conventional semiconductor device using a high-resistance element includes a well
101
doped with N type impurity, an element separating insulation film
102
formed from a main surface of the well
101
to the prescribed depth, a high-resistance element
103
consisting of a diffusion layer of P type impurity and surrounded by the element separating insulation film
102
, contact plugs
104
a
and
104
b
connected to the high-resistance element
103
, an interlayer insulation film
105
in which the contact plugs
104
a
and
104
b
are buried, interconnection layer
106
a
formed on the interlayer insulation film
105
and connected to the contact plug
104
a
, an interconnection layer
106
b
connected to the contact plug
104
b
, an interlayer insulation film
107
formed to cover the interconnection layers
104
a
and
104
b
respectively, and an upper interconnection layer
108
formed on the interlayer insulation film
107
.
As shown in
FIGS. 16
to
18
, resistance value of the high resistance element
103
is determined by resistance value per unit area and dimension of the P type impurity diffusion layer. For example, the resistance value R of the high-resistance element
103
may be expressed as follows:
R=R
p
×L/W
where R
p
is resistance value per unit area of the P type impurity diffusion layer, L is the length of the P type impurity diffusion layer, and W is the width of the P type impurity diffusion layer. When R is constant, the resistance value of the high-resistance element
103
fluctuates corresponding to the degree of effect, as indicated by arrows
125
in
FIG. 18
, from changes in potential of the upper interconnection layer
108
.
More specifically, the structure shown in
FIG. 18
including the upper interconnection layer
108
, interlayer insulation films
105
,
107
, and the high-resistance element
103
is similar to the structure of an MOS transistor including a gate electrode, a gate insulation film and a channel region. As such, fluctuation of the potential of upper interconnection layer
108
between “H” and “L” changes state of charges distributed in high-resistance element
103
configured with P type impurity diffusion layer. As a result, the resistance value of high-resistance element
103
changes, which in turn changes the amount of current flowing through high-resistance element
103
.
One possible technique to solve the above mentioned problem is a structure in which interconnection layer
106
b
is formed to substantially cover the region above high-resistance element
103
, as shown in
FIGS. 19
to
21
. According to the structure, even when the amount of current flowing through upper interconnection layer
108
changes, the portion of interconnection layer
106
b
formed above high-resistance element
103
suppresses electrical effect of the upper interconnection layer
108
as indicated by arrows
125
. Thus, the resistance value of high-resistance element
103
is prevented from fluctuation.
Specifically, in a semiconductor device shown in
FIGS. 19
to
21
, interconnection layer
106
b
extends to the region between the contact plug
104
a
and contact plug
104
b
directly above the high-resistance element
103
. Thus, the interconnection layer
106
b
shields high-resistance element
103
from the effect from changes in potential of the upper interconnection layer
108
. It is accomplished by the fact that the potential of the upper interconnection layer
106
b
does not fluctuate as that of the upper interconnection layer
108
and is always identical to that of the contact plug
104
b
connected to high-resistance element
103
.
In the above mentioned semiconductor device, however, the extending length of interconnection layer
106
a
and that of interconnection layer
106
b
are different. In other words, the interconnection layer
106
a
and the interconnection layer
106
b
are asymmetric to high-resistant element
103
. Thus, electric effects on the resistance value of high-resistance element
103
caused by interconnection layer
106
a
and that caused by interconnection layer
106
b
are different. Therefore, depending on whether an interconnection layer electrically connected to the high potential electrode side is connected to interconnection layers
106
a
or
106
b
, the resistance value of high-resistance element
103
, and in effect the amount of the current flowing therethrough, will be different. As a result, on designing a semiconductor device, there has been a limitation on degree of freedom in the layout of an interconnection layer connected to the high potential electrode side, which is to be electrically connected to high-resistance element
103
via interconnection layers
106
a
and
106
b.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device with improved degree of freedom on designing layout of an interconnection layer electrically connected to a high-resistance element, or an interconnection connected to conductive unit, via contact plugs.
A semiconductor device using a resistance element according to a first aspect of the present invention includes a semiconductor substrate, a resistance element formed above or within the semiconductor substrate, an interlayer insulation film formed on the resistance element, a first contact hole penetrating vertically the interlayer insulation film and connected to the resistance element, a second contact hole penetrating vertically the interlayer insulation film and connected to the resistance element, a first interconnection layer formed on the interlayer insulation film and connected to the first contact hole, and a second interconnection layer formed on the interlayer insulation film and connected to the second contact hole. And above the region between the first and second contact holes, the first and the second interconnection layers are formed symmetrical to the prescribed plane perpendicular to the semiconductor substrate, or formed into layers of identical thickness and at the same height and in point symmetry on a prescribed plane parallel to the semiconductor substrate.
According to the above structure, above the region between the first and second contact holes, respective electrical effects to the resistance value of the resistance element by the first and the second interconnection layers become equivalent, thus the degree of freedom is improved on designing interconnection layers respectively connected to the first and second interconnection layers.
A semiconductor device using a resistance element according to a second aspect of the present invention includes a semiconductor substrate, a resistance element formed above the semiconductor substrate, an interlayer insulation film formed under the resistance element, a first contact hole penetrating vertically the interlayer insulation film and connected to the resistance element, a second contact hole penetrating vertically the interlayer insulation film and connected to the resistance
Clark Jasmine
McDermott & Will & Emery
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