Semiconductor device

Details Semiconductor device Semiconductor device

2001-09-18

2003-10-14

Tran, Thien (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000, C257S386000, C257S412000, C257S616000, C257S384000

Reexamination Certificate

active

06633070

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device provided with a field-effect transistor capable of fast operation as well as a method of manufacturing the same.
2. Description of the Background Art
A conventional semiconductor device provided with a field-effect transistor is manufactured as follows. As shown in
FIG. 32
, an element isolating region
103
and a well
102
are formed at a silicon substrate
101
or an SOI (Silicon on Insulator). Then, a silicon oxide film
104
, which will form a gate insulating film, is formed on silicon substrate
101
.
A polycrystalline silicon film, which is not shown and will form a gate electrode, is formed on silicon oxide film
104
. A silicon oxide film (not shown) is formed on the polycrystalline silicon film. Predetermined photolithography and treatment are effected on the silicon oxide film to form a hard mask
106
. Anisotropic etching is effected on the polycrystalline silicon film masked with hard mask
106
to form a gate electrode
105
.
Then, as shown in
FIG. 33
, ions producing a predetermined conductivity type are implanted into well
102
masked with hard mask
106
and gate electrode
105
so that pocket regions
108
a
and
108
b
as well as extension regions
107
a
and
107
b
are formed. Thereafter, a heat treatment is performed. Then, a silicon oxide film and a silicon nitride film covering hard mask
106
and gate electrode
105
are successively formed on silicon substrate
101
.
Then, as shown in
FIG. 34
, anisotropic etching is effected on the silicon oxide film and silicon nitride film thus formed so that silicon oxide films
109
, which form sidewall insulating films, and silicon nitride films
110
are formed on the side surfaces of gate electrode
105
and hard mask
106
.
Then, as shown in
FIG. 35
, a silicon selective epitaxial growth method is perform to form silicon layers
111
a
and
111
b
on exposed surfaces of extension regions
107
a
and
107
b
, respectively. Then, as shown in
FIG. 36
, impurities producing a predetermined conductivity type are implanted into silicon layers
111
a
and
111
b
by an ion implanting method, as shown in FIG.
36
. Thereafter, heat treatment is effected form source/drain regions
112
a
and
112
b
at well
102
.
In this manner, a major portion of the semiconductor device provided with the field-effect transistors is formed. In the method of manufacturing the semiconductor device described above, impurities implanted into silicon layers
111
a
and
111
b
are diffused by the heat treatment into the regions of silicon substrate
101
(well
102
) so that source/drain regions
112
a
and
112
b
are formed. Thereby, source/drain regions
112
a
and
112
b
have a relatively small depth, which improves the short-channel characteristics of the field-effect transistor.
However, the method of manufacturing the semiconductor device described above suffers from the following problem. Since silicon layers
111
a
and
111
b
are formed on the surface of silicon substrate
102
(extension regions
107
a
and
107
b
), a large fringing capacitance (parasitic capacitance) occurs between silicon layers
111
a
and
111
b
and gate electrode
105
. As a result, it is difficult to improve further the operation speed of the field-effect transistor.
SUMMARY OF THE INVENTION
The invention has been developed for overcoming the above problem, and it is an object of the invention to provide a semiconductor device capable of faster operation. Another object of the invention is to provide a method of manufacturing the semiconductor device.
A semiconductor device according to an aspect of the invention includes a gate electrode, sidewall insulating films and source/drain regions. The gate electrode is formed on a surface of a semiconductor substrate with a gate insulating film therebetween. The sidewall insulating films are formed on opposite side surfaces of the gate electrode, respectively. The source/drain regions are formed on one and the other of regions of the semiconductor substrate spaced from each other with the gate electrode and the sidewall insulating films therebetween, and each include a portion formed at the surface of the semiconductor substrate and a raised portion formed on the surface of the portion formed at the semiconductor substrate surface. The sidewall insulating film is provided at its portion located between the raised portion and the gate electrode with a void.
According to the above structure, the void is formed in the portion of the sidewall insulating film located between the raised portion of each of the source/drain regions and the gate electrode in the field-effect transistor. Since the dielectric constant of the void is much lower than that of a bulk of the sidewall insulating film, parasitic capacitances (fringing capacitances) between the source/drain regions and the gate electrode are smaller than that in a structure not provided with the void in the sidewall insulating film. As a result, the operation speed of the field-effect transistor can be improved.
Preferably, the raised portion has a height substantially two or more times larger than a thickness of the sidewall insulating film on the surface of the semiconductor substrate.
This can suppress such a situation that a material gas reaches a deep position in the space between the raised portion and the gate electrode when forming the film for the sidewall insulating film, and thus allows easy formation of the void in this portion.
Preferably, the gate electrode has a wide portion located closer to the raised portion.
This structure reduces a distance between the raised portion and the wide portion of the gate electrode, and allows easy formation of the void between the lower portion of the raised portion and the lower portion of the gate electrode.
More preferably, the gate electrode is formed of at least two layers, and the upper layer of the two layers includes the wide portion.
In the above structure, the gate electrode is formed of the two layers having different characteristics. Therefore, the wide portion can be easily formed.
In the above structure, it is preferable that the upper layer of the gate electrode is made of silicon, and the lower layer is made of silicon germanium, or that the upper layer of the gate electrode contains metal, and the lower layer contains a semiconductor layer.
More preferably, the wide portion has the lower end located at the level equal to or lower than the top surface of the raised portion.
This structure allows easy formation of the void at the level lower than the lower end of the wide portion.
Preferably, the semiconductor device includes an interlayer insulating film formed on the semiconductor substrate and covering the sidewall insulating films and the source/drain regions, and the interlayer insulating film has the top surface located closer to the gate electrode.
This structure further reduces the distance between the top portion of the interlayer insulating film and the gate electrode, and allows easy formation of the void having relatively large sizes and located in and between the lower and upper portions of the gate electrode when forming the sidewall insulating film.
More preferably, the gate electrode is made of metal.
This can reduce the resistance of the gate electrode.
A method of manufacturing a semiconductor device according to another aspect of the invention includes the following steps. A gate electrode is formed on a surface of a semiconductor substrate. A dummy sidewall insulating film is formed on each of the opposite side surfaces of the gate electrode. Impurity regions partially forming source/drain regions are formed on one and the other of regions of the semiconductor substrate spaced from each other with the gate electrode and the sidewall insulating films therebetween. Raised portions partially forming the source/drain regions are formed on the surfaces of the impurity regions,

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