Semiconductor device

Details Semiconductor device Semiconductor device

1998-05-20

2003-10-14

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S197000, C257S378000, C257S565000, C438S202000, C438S234000

Reexamination Certificate

active

06633069

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including a bipolar transistor and a Bi-CMOS LSI in which the bipolar transistor and a CMOS transistor are mounted on the same chip.
In recent years, a high-performance silicon bipolar transistor technology has increasingly been developed in order to actualize a high-speed and low power consumption LSI, and there has been proposed a technology of constructing a transistor exhibiting high-speed/high frequency characteristics using, a non-selective epitaxial technique.
Furthermore, in recent years, there has been seen a progress of a development of a Bi-CMOS LSI (Bipolar-Complementary Metal Oxide Semiconductor Large Scale Integrated Circuit) which aims at mobile communications technology, etc. Especially, a portable communication terminal is required to be high performance, low power consumption and, in addition, low price, and hence it is a vital question to ensure a product competing strength by thoroughly reducing the costs.
A structure and a method of manufacturing a high-speed silicon bipolar transistor according to the prior art will be explained with reference to FIG.
1
.
N-type layers
61
and
64
serving as collectors isolated by element isolation regions
62
and
63
on a p-type silicon substrate
60
containing a high-concentration n-type buried layer (not illustrated), and a silicon single crystal layer
65
which acts as a base region is formed on the collector region
61
and a collector lead-out region
64
, and a polycrystalline silicon layer
66
which acts as a base lead-out region is formed on the silicon oxide layers
62
and
63
. On the base region
65
, an etching stopper film
67
having an opening
83
in the center thereof, and corresponding to the opening, an emitter region
85
is formed in the base region
65
. In the peripheral of the etching stopper
67
, a base lead-out polysilicon electrode
68
is formed on the base lead-out region
66
, and a collector lead-out polysilicon electrode
69
is formed above the external collector lead-out region
64
. On the etching stopper film
67
, a side wall
82
is formed and the inner surface thereof defines the opening
83
. On the polysilicon film
68
, a silicon oxide film
70
and a silicon nitride film
80
are formed such that their ends reach the side wall
82
, and a polycrystalline film
80
fills the opening
83
from the upper surface of nitride film
80
. An insulating inter-layer film
86
is formed on the whole surface, contact holes
88
,
89
and
87
are formed respectively corresponding, to the base lead-out region
68
, external collector lead-out region
69
and a polysilicon film
84
as an external emitter lead-out region.
Next, a manufacturing method of the above-mentioned conventional high-speed bipolar transistor will be explained with reference to FIG.
1
.
First of all, the n-type layers
61
,
64
serving as the collector are epitaxially grown on the p-type silicon substrate
60
containing a high-concentration p-type buried layer (not illustrated). Then, through patterning, process of an elementisolation region, an oxide layer depositing process and an etch-back process, an elementisolation of the transistor is effected by the oxide layer
63
, and the oxide layer
62
isolates and separates the collector region
61
from the external collector lead-out region
64
.
Subsequently, a silicon crystalline layer is grown over the silicon single crystal
65
serving as a base region is grown on the collector region
61
, and the polysilicon
60
serving as the base lead-out region is grown the oxide layer
62
.
Next, a composite layer consisting of a nitride layer and an oxide layer is deposited over the whole surface, and predetermined patterning is executed on the base region
65
, thereby providing the etching stopper layer
67
.
Subsequently, there are deposited the polycrystalline silicon
68
and the polycrystalline silicon
69
which respectively serve as a base lead-out region and a collector lead regions. Then, a p-type impurity is ion-implanted into a base electrode, while an n-type impurity is ion-implanted into the collector lead-out region. Further, the oxide layer
70
and the nitride layer
80
are sequentially deposited by a CVD (Chemical Vapor Deposition) method. Thereafter a first opening
71
for forming an emitter region is opened by an RIE (Reactive Ion Etching) method, and simultaneously the base lead-out polysilicon electrode
68
is separated from the collector lead-out polysilicon electrode
69
. Thereafter, the oxide layer is deposited by the CVD method, and the side wall spacer
82
is formed by the RIE method. Subsequently, the etching stopper layer
67
is wet-etched so as not to damage the base region
65
, thereby forming a second opening
83
.
Next, polycrystalline silicon
84
is deposited, an n-type impurity is ion-implanted, and the impurity is diffused in a solid phase within the base region
65
contiguous to the polycrystalline silicon layer
84
by effecting a thermal treatment, thereby providing an emitter region
85
. Subsequently, the polycrystalline silicon
84
containing the n-type impurity is subjected to patterning in a predetermined configuration.
Next, an inter-layer insulating film
86
is deposited by the CVD method and, with this serving as an etching mask, after a photo resist has been subjected to the patterning in a predetermined shape by photolithography, the base contact hole
88
, the emitter contact hole
87
and collector contact hole
89
are formed by the RIE method. Thereafter, metal wirings are formed by the conventional technique, thus completing the transistor.
In the transistor manufactured by the method described above, an extremely thin base layer can be formed, and hence it is feasible to obtain a higher cut-off frequency than in the transistor having the base layer formed by the conventional ion implanting and diffusion techniques.
There arise, however, the following problems inherent in the bipolar transistor manufactured by the method described above.
To be specific, an electric current flows from an opening
88
to the base lead-out electrode via the polycrystalline silicon
68
, the polycrystalline silicon
66
and the single crystal silicon
65
to just under a emitter diffused layer
85
performing a bipolar operation, and therefore a base resistance value increases. Further, a depth of the opening with respect to an emitter opening width, i.e., an aspect ratio, is large, and consequently a base/collector capacity value with respect to an emitter resistance value and an emitter areal size increases. Then high frequency characteristics such as fmax and Ga etc. and noise characteristics such as Nf etc. decline, and besides an emitter plug effect occurs with the result that an emitter base junction can not be obtained well and a yield of the bipolar transistor decreases.
Moreover, the emitter diffused layer width is defined by the side wall spacer formed by the RIE after the emitter opening has been formed, and hence a controllability declines, resulting in such a problem that device characteristics become ununiform.
Further, Bi-CMOS LSI is structured such that a high-performance bipolar transistor and a MOS type field effect transistor are constructed on the same silicon substrate.
A prior art method of manufacturing a semiconductor integrated circuit device components of which are the bipolar transistor as an active element and the MOS type field effect transistor, will be explained with reference to the drawings by way of one example of the LSI discussed above.
To start with, as illustrated in
FIG. 2
, a thermal oxide layer
203
is provided by thermal oxidation on a silicon substrate
201
, and subsequently the oxide layer
203
existing exactly on a region to be formed with an n
−
buried layer, is removed by resist patterning based on the photolithography and by an HF series solution. Thereafter, an oxide layer
204
containing antimony (Sb) is deposited on a wafer

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