Semiconductor device

Details Semiconductor device Semiconductor device

1997-12-15

2003-02-11

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S408000, C257S345000

Reexamination Certificate

active

06518625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device which is reduced in resistance by a salicide structure and a method of fabricating the same.
2. Description of the Background Art
In recent years, LSIs are refined due to the development of designs of integrated circuits and process techniques to enable fabrication of high-density integrated circuits, while high-speed operations are strongly required particularly in logic circuits. Reduction of resistance is effective means for attaining a high-speed operation, and reduction of contact resistance is attained by a salicide (self-aligned silicide) structure provided with low-resistance layers on contact parts of a source/drain and a gate electrode.
FIG. 55
is a sectional view of an element showing a conventional semiconductor device of a salicide structure. A p well
103
is formed on a surface of a semiconductor substrate
101
. A field oxide film
102
is formed on an isolation region of the semiconductor substrate
101
, so that a MOS (metal oxide semiconductor) transistor is formed in an active region which is enclosed with the field oxide film
102
.
This MOS transistor has a pair of n-type extension layers
109
, a pair of sources/drains
1010
, a gate insulator film
106
, and a gate electrode
107
. The pair of n-type extension layers
109
are formed on the surface of the semiconductor substrate
101
at a prescribed distance, and the sources/drains
1010
are also formed on the surface of the semiconductor substrate
101
to be adjacent to the n-type extension layers
109
. The n-type extension layers
109
and the sources/drains
1010
form an LDD (lightly doped drain) structure. The gate electrode
107
is formed on a region held between the pair of n-type extension layers
109
through the gate insulator film
106
, and side surfaces of the gate electrode
107
are covered with side walls
108
.
Metal silicide layers
1011
are formed on the gate electrode
107
and the sources/drains
1010
, to be in contact therewith respectively.
A channel cut injection layer
104
is formed to be in contact with the lower surface of the field oxide film
102
in the isolation region and positioned at a prescribed depth from the surface of the semiconductor substrate
101
in the active region. Further, a channel injection layer
105
is formed in the active region on a shallower position than the channel cut injection layer
104
.
An interlayer isolation film
1016
is formed to cover the MOS transistor, and provided with contact holes reaching the metal silicide layers
1011
. Contacts
1017
are formed to fill up the contact holes.
As shown in
FIG. 55
, the metal silicide layers
1011
are formed between the contacts
1017
and the sources/drains
1010
, thereby reducing the resistance. The metal silicide layers
1011
may be prepared from a metal such as Co, Ni, Ti, W or Pt.
In the conventional semiconductor device, however, it is so difficult to completely;control the shape of each metal silicide layer
1011
that the same may extend into a portion under the field oxide film
102
along the boundary between the field oxide film
102
and each source/drain
1010
, as shown in FIG.
56
. This phenomenon remarkably takes place particularly when the metal silicide layer
1011
is prepared from a metal such as Co or Ni serving as a diffusion species when reacting with silicon.
Thus, the distance between a pn junction formed by each source/drain
1010
and the p well
103
and an end portion of the metal silicide layer
1011
may be reduced, or the metal silicide layer
1011
may project beyond the source/drain
1010
, to result in direct connection between the metal silicide layer
1011
and the p well
103
, the channel cut injection layer
104
or the channel injection layer
105
formed in the semiconductor substrate
101
.
When a metal film is formed after formation of an isolation insulator film, an end portion of the field oxide film
102
may be eroded by wet etching performed before formation of the metal film for removing a natural oxide film, as shown in FIG.
57
.
When the end portion of the field oxide film
102
is eroded, a surface part of the semiconductor substrate
101
may be exposed on this portion, to result in direct connection between each metal silicide layer
1011
and the p well
103
, the channel cut injection layer
104
or the channel injection layer
105
formed in the semiconductor substrate
101
, or reduction of: the distance between the pn junction formed by each source/drain
101
and the p well
103
and the end portion of the metal silicide layer
1011
.
Also when trench isolation is employed, a metal silicide layer
1011
may extend into a portion under an end portion of a buried oxide film
1018
as shown in
FIG. 58
or the end portion of the buried oxide film
1018
may be eroded as shown in
FIG. 59
, if the metal silicide layer
1011
is prepared from Co or Ni. Thus, the distance between a pn junction formed by a source/drain
1010
and a p well
103
and an end portion of the metal silicide layer
1011
may be reduced or the metal suicide layer
1011
may project beyond the source/drain
1010
, to result in direct connection between the metal silicide layer
1011
and the p well
103
, a channel cut injection layer
104
or a channel injection layer
105
formed in the semiconductor substrate
101
.
If the metal silicide layer
1011
projects beyond the source/drain
1010
to be directly connected with the p well
103
, the channel cut injection layer
104
or the channel injection layer
105
, a leakage current flows between the source/drain
1010
and the p well
103
upon application of a voltage, to extremely reduce the reliability of the element.
Also when the distance between the pn junction formed by the source/drain
1010
and the p well
103
and the metal silicide layer
1011
is reduced a depletion layer grows due to voltage application, and hence the metal silicide layer
1011
is disadvantageously electrically connected with the p well
103
to increase the leakage current and reduce the reliability of the element.
To this end, low-concentration n-type impurity layers
1091
are formed to attain reduction of the leakage current, as shown in FIG.
60
. This technique is disclosed in U.S. Pat. No. 4,949,136, for example.
In such a structure, however, punch-through disadvantageously takes place if the low-concentration n-type impurity layers
1091
are deeply formed for preventing projection of metal silicide layers
1011
on end portions of a field oxide film
102
.
In this structure, further, punch-through readily takes place if side walls
108
and
1081
are reduced in thickness. If the side walls
108
and
1081
are increased in thickness, on the other hand, exposed surface parts of sources/drains
1010
are so reduced that the resistance is disadvantageously increased due to insufficient contact.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which can reduce a junction leakage current while maintaining a sufficient contact width without increasing the depth of a source/drain, for attaining a high-speed operation with no deterioration of its element characteristics following refinement, and a method of fabricating the same.
A semiconductor device according to the present invention comprises a first conductivity type semiconductor substrate, an isolation insulator film which is formed on an isolation region of a major surface of the semiconductor substrate, a second conductivity type source and a second conductivity type drain which are formed at
an active region enclosed with the isolation region on the major surface of the semiconductor substrate, a gate electrode which is formed on a major surface of the active region through a gate insulator film, metal compound layers which are formed on surfaces of the source, the drain and the gate electrode respectively, and

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