Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-01-16
2003-12-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230060, C365S201000, C365S226000, C365S189011
Reexamination Certificate
active
06657904
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor memory device, such as DRAM, which is subjected to a screening test.
2. Description of the Related Art
A screening test (also called an accelerated aging test) is conducted for semiconductor memory devices, such as DRAM, before the IC chips are built into in the packages, in order to eliminate the devices that yield early failures among the manufactured products. When the screening test is conducted, a raised power-source voltage, equivalent to or higher than the rated voltage, is applied to the semiconductor device to be tested under a high-temperature condition. Further, the internally produced voltage of the semiconductor device being tested is increased to a level higher than the level in the normal mode operation. During the screening test, the semiconductor device being tested suffers such voltage and temperature stresses.
If the power-source voltage and the internally produced voltage are too high, a breakdown of the semiconductor device occurs during the screening test. If the power-source voltage and the internally produced voltage are too low, the time needed to finish the screening test becomes long and the cost becomes high. Hence, it is necessary to generate these voltages at proper levels in the screening test. In particular, the internally produced voltage must be set to a proper level that is suited to the transistors of the memory cells that are the major portion of the semiconductor memory device and are likely to yield the initial failure.
However, in a DRAM device of the word-line negative reset type wherein a non-selected word line is reset to a negative voltage, it is difficult to set, when performing the screening test, the internally produced voltage to the level suited to the transistors of the memory cells. A description will now be provided of the problem concerning the DRAM device of the word-line negative reset type with reference to FIG.
1
.
FIG. 1
shows a portion of the DRAM device of the word-line negative reset type which includes a memory cell provided adjacent to a word line. As shown in
FIG. 1
, the memory cell includes a cell transistor
10
and a cell capacitor
11
. The cell transistor
10
has a gate connected to the word line “WL”. The cell capacitor
11
is connected to the bit line “BL” through the cell transistor
10
. A predetermined voltage “VCP” is supplied to one end of the cell capacitor
11
.
The predetermined voltage “VCP” may be set so that it is equal to either a ground voltage “VSS” or an internally produced voltage “(VCC−VSS)/2”. In the following, suppose that the predetermined voltage “VCP” is equal to the ground voltage “VSS” (VCP=VSS).
In the memory cell in
FIG. 1
, a driver circuit, which is formed by a CMOS (complementary metal oxide semiconductor) inverter including a p-channel MOS transistor
12
(which is called the PMOS transistor
12
) and an n-channel MOS transistor
13
(which is called the NMOS transistor
13
), is connected to the word line WL. The driver circuit has an input connected to a word decoder (not shown in FIG.
1
).
A raised voltage VPP is internally produced in the DRAM device from an external power-source voltage, and the raised voltage VPP is supplied to the source of the PMOS transistor
12
. Further, a negative voltage VNWL is internally produced in the DRAM device, and the negative voltage VNWL is supplied to the source of the NMOS transistor
13
.
During the operation of the DRAM device in the normal mode, when the memory cell
10
is selected (or when the word line WL is selected), the selected word line WL is set to the raised voltage VPP. When the memory cell
10
is not selected (or when the word line WL is not selected), the non-selected word line WL is set to the negative voltage VNWL. In other words, the voltage of the word line WL is switched between the raised voltage VPP and the negative voltage VNWL. When the voltage of the word line WL is at the raised voltage VPP, the gate-to-source voltage of the NMOS transistor
13
is set to the level (VPP−VNWL). When the voltage of the word line WL is at the negative voltage VNWL, the gate-to-source voltage of the PMOS transistor
12
is set to the level (VPP−VNWL). The back bias of the PMOS transistor
12
is set to the raised voltage VPP. The back bias of the NMOS transistor
13
is set to the negative voltage VNWL.
The gate-to-source voltage (or the gate-to-drain voltage) of the cell transistor
10
is set to the level (VPP−VSS). The back bias of the cell transistor
10
is set to the ground voltage VSS.
In the DRAM device of the above type, the gate-to-source voltage of the NMOS transistor
13
or the gate-to-source voltage of the PMOS transistor
12
is set to the level (VPP−VNWL), while the gate-to-source voltage of the cell transistor
10
is set to the level (VPP−VSS). Hence, the voltage stress exerted on the PMOS transistor
12
or the NMOS transistor
13
is higher than the voltage stress exerted on the cell transistor
10
by the difference (VSS−VNWL). Such unbalanced voltage stress, which is present at the CMOS inverter, is similarly exerted onto the neighboring circuit of the cell transistor
10
connected to the word line WL, such as the word decoder.
Also when the screening test is performed, the voltage stress exerted on the CMOS inverter or the neighboring circuit of the cell transistor (e.g., the word decoder) is higher than the voltage stress exerted on the cell transistor
10
. In such conditions, it is difficult for the DRAM device of the above type to set, when performing the screening test, the internally produced voltage to the level suited to the transistors of the DRAM device. Ordinarily, the time needed to finish the screening test with respect to the DRAM device of the above type becomes long, and the cost becomes high. In order to eliminate this problem, if the voltage stress exerted on the cell transistor
10
is increased to allow speedy performance of the screening test, the voltage stress exerted on the CMOS inverter or the word decoder becomes excessively high and a breakdown of the DRAM device element may occur during the screening test.
As described above, the DRAM device of the word-line negative reset type has the problem in that the voltage stress exerted on the CMOS inverter or the word decoder is different from the voltage stress exerted on the cell transistor. Therefore, it is difficult to efficiently perform the screening test by exerting the same voltage stress on all the elements of the DRAM device of the word-line negative reset type.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved semiconductor device in which the above-described problems are eliminated.
Another object of the present invention is to provide a semiconductor device which is configured to exert the same voltage stress on the elements of the semiconductor device when performing the screening test, in order to efficiently carry out the screening test.
The above-mentioned objects of the present invention are achieved by a semiconductor device comprising: a voltage generator which sets a voltage of a non-selected word line to a negative voltage when the semiconductor device is set in a normal mode; and a circuit which resets the voltage of the non-selected word line to a ground voltage when the semiconductor device is set in a predetermined mode.
The above-mentioned objects of the present invention are achieved by a semiconductor device in which a voltage of a non-selected word line is set at a first negative voltage, the semiconductor device comprising: a first circuit which resets the voltage of the non-selected word line to a ground voltage when the semiconductor device is set in a first mode; and a second circuit which sets the voltage of the non-selected word line at a second negative voltage different from the first negative voltage when the semiconductor device is set in a secon
Elms Richard
Fujitsu Limited
Nguyen Nam
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