Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
2002-03-27
2003-10-14
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S678000
Reexamination Certificate
active
06633080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to the structure of a power transistor.
2. Description of the Background Art
FIG. 7
is a plan view exemplifying the appearance of a transistor
100
as a semiconductor device in the background art. The transistor
100
is of a TSSOP (thin shrink small outline package) type in external form. A power transistor of the TSSOP type belonging to surface mounting package has a height of approximately 1.1 mm in external shape and therefore, it is preferably used as a semiconductor element in a portable device such as a mobile telephone.
In appearance, the transistor
100
includes a resin package
20
and groups
30
,
39
of outer leads. The resin package
20
has a first side surface
23
and a second side surface
24
. Outer leads belonging to the groups
30
and
39
protrude from the first side surface
23
and the second side surface
24
, respectively.
FIG. 8
is a plan view exemplifying the internal structure of the transistor
100
. To provide description of the internal structure of the resin package
20
, only the outline thereof is shown in a dashed line.
FIG. 9
is a cross-sectional view of the transistor
100
taken along a cutting plane line A—A in FIG.
7
.
The transistor
100
is provided with a semiconductor chip
1
, a lead frame
5
and bonding wires
4
inside the resin package
20
. The lead frame
5
includes the group
39
of outer leads at one end and a sheet-like portion
51
for holding the semiconductor chip
1
mounted thereon from the side of a bottom surface
25
of the resin package
20
. One end of each bonding wire
4
is bonded to the semiconductor chip
1
from the side of a top surface
21
of the resin package
20
and the other end thereof is connected to one of the outer leads of the group
30
.
The group
30
includes outer leads
31
,
32
,
33
each serving as an external source electrode S and an outer lead
34
serving as an external gate electrode G. The group
39
includes outer leads
35
,
36
,
37
and
38
each serving as an external drain electrode D.
By bonding the semiconductor chip
1
to the lead frame
5
, establishing connection by the bonding wires
4
and performing sealing with a resin using a known technique, the transistor
100
including the resin package
20
is completed.
Similar to the usual plastic molding, the resin package
20
to be formed by sealing is ejected and detached from a molding die thereof by an ejector pin. At this time, a recessed portion is formed on the top surface
21
of the resin package
20
as an ejector pin recess site
22
.
When the transistor
100
is a power transistor, it is desirable that the bonding wires
4
are independently connected to the outer leads
31
,
32
and
33
from separate positions on the semiconductor chip
1
, thereby allowing improvement in tolerance for current breakdown and reduction in on-state voltage. For such connection using the plurality of bonding wires
4
, it is still desirable that the wires
4
are each suspended above the semiconductor chip
1
at a greatest possible height.
The thickness of the resin package
20
is small due to the TSSOP configuration of the transistor
100
in external form. Further, the semiconductor chip
1
and the group
30
of outer leads are connected by the bonding wires
4
on the side of the top surface
21
of the resin package
20
. Accordingly, when the bonding wires
4
are each suspended above the semiconductor chip
1
at a great height, it is likely that the bonding wires
4
may be exposed from the top surface
21
to the outside of the resin package
20
resulting from the presence of the ejector pin site
22
.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor device includes a semiconductor chip, a lead frame, at least one connector, a plurality of second outer leads and a package. In the semiconductor device according to the present invention, the semiconductor chip includes a first surface, a second surface and a semiconductor element. The semiconductor element has a first current electrode and a second current electrode. The first surface holds the first current electrode. The second surface holds the second current electrode and is opposite to the first surface. Further, in the semiconductor device according to the present invention, the lead frame includes a sheet-like portion and an end portion. The sheet-like portion is connected to the first current electrode on the first surface of the semiconductor chip. The end portion has a plurality of first outer leads. Still further, in the semiconductor device according to the present invention, the plurality of second outer leads are connected to the second current electrode by the at least one connector. Yet further, in this semiconductor device, the package includes a first side surface, a second side surface, a first surface, a second surface and a recessed portion. The first side surface holds the plurality of first outer leads arranged thereon. The second side surface holds the second outer leads arranged thereon and is opposite to the first side surface. The first surface is located farther from the semiconductor chip than the lead frame. The second surface is located farther from the semiconductor chip than the at least one connector and opposite to the first surface of the package. The recessed portion is formed on the second surface of the package on the side of the first side surface.
Preferably, the at least one connector is a metal plate or a plurality of metal wires.
Preferably, the semiconductor element further has a gate electrode. Further, the semiconductor device also includes a third outer lead arranged on the second side surface of the package and connected to the gate electrode.
According to the present invention, a method of manufacturing a semiconductor device includes steps of (a) to (c). In the step of (a), a semiconductor is provided. The semiconductor includes a semiconductor chip. The semiconductor chip includes a semiconductor element, first and second surfaces. The semiconductor element has a first current electrode and a second current electrode. The first electrode holds the first current electrode. The second surface holds the second current electrode and is opposite to the first surface. The semiconductor further includes a lead frame. The lead frame has a sheet-like portion and an end portion. The sheet-like portion is connected to the first current electrode on the first surface of the semiconductor chip. The end portion has a plurality of first outer leads. The semiconductor further includes at least one connector and a plurality of second outer leads. The plurality of second outer leads are connected to the second current electrode by the at least one connector. In the step of (b), the semiconductor chip, the lead frame and the at least one connector is sealed with a package. The package includes a first side surface, a second side surface, a first surface and a second surface. The first side surface holds the plurality of outer leads arranged thereon. The second side surface holds the second outer leads arranged thereon and is opposite to the first side surface. The first surface is located farther from the semiconductor chip than the lead frame. The second surface is located farther from the semiconductor chip than the at least one connector and opposite to the first surface of the package. In the step of (c), the package is ejected from a molding die by an ejector pin on the second surface of the package on the side of the first side surface. Thus, detaching the package from the molding die.
According to the present invention, it is possible to reduce the outer thickness of the semiconductor device. Further, regardless of the presence of the ejector pin site, connection between the second current electrode and the plurality of second outer leads by the connector is realized that allows improvement in tolerance for current breakdown and reduction in on-state voltage.
I
Cruz Lourdes
Mitsubishi Denki & Kabushiki Kaisha
Talbott David L.
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