Semiconductor device

Details Semiconductor device Semiconductor device

2000-04-20

2003-03-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S241000

Reexamination Certificate

active

06531747

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a static random access memory (hereinafter referred to as “SRAM”) cell.
2. Description of the Prior Art
In recent years, it is important to save energy for and reduce the voltage of a semiconductor device built in a portable device, so that the portable device can be driven by a battery as long as possible. Following this, an SRAM operable at a low voltage with low power consumption is increasingly demanded.
In order to satisfy such requirements, a CMOS memory cell is employed as the memory cell of the SRAM. The CMOS memory cell is formed by four n-channel MOS transistors and two p-channel MOS transistors.
In general, two access transistors and two driver transistors are employed for an SRAM memory cell. For the CMOS memory cell, two load transistors are further employed as load elements in addition to these transistors.
A conventional CMOS memory cell is now described with reference to FIG.
19
. Referring to
FIG. 19
, element forming regions
120
a
,
120
b
,
120
c
and
120
d
separated by a field isolation film
103
are formed on the surface of a silicon substrate. An access transistor T
1
and a driver transistor T
3
are formed on the element forming region
120
a.
An access transistor T
2
and a driver transistor T
4
are formed on the element forming region
120
b
. A load transistor T
5
is formed on the element forming region
120
c
. A load transistor T
6
is formed on the element forming region
120
d.
A gate electrode
104
c
is formed across the element forming regions
120
a
and
120
b
. A gate electrode
104
a
is formed across the element forming regions
120
a
and
120
c
. A gate electrode
104
b
is formed across the element forming regions
120
b
and
120
d
. Contact holes
112
a
,
112
b
and
112
c are formed to expose the surface of the element forming region
120
a.
Contact holes
112
d
,
112
e
and
112
f
are formed to expose the surface of the element forming region
120
b
. Contact holes
112
g
and
112
h
are formed to expose the surface of the element forming region
120
c
. Contact holes
112
i
and
112
j
are formed to expose the surface of the element forming region
120
d.
Contact holes
112
k
and
112
m
are formed to expose the surface of an n well
102
b
. A gate electrode
104
d
belongs to another memory cell adjacent to this memory cell. A plurality of such memory cells are formed on a silicon substrate in a single SRAM.
An exemplary method of manufacturing the aforementioned memory cell is now described with reference to sectional views taken along the line XX—XX in FIG.
19
. Referring to
FIG. 20
, a p well
102
a
is formed on a prescribed region of a silicon substrate
101
. The gate electrodes
104
a
and
104
d
are formed on the surface of the p well
102
a
through a gate insulator film
105
with masks of on-gate insulator films
106
a
and
106
b.
An impurity such as phosphorus, for example, is injected through the gate electrodes
104
a
and
104
d
and the on-gate insulator films
106
a
and
106
b
serving as masks, thereby forming an n
−
drain region
109
a
and an n
−
source region
109
b.
Referring to
FIG. 21
, a silicon oxide film (not shown) is formed by CVD, for example, to cover the gate electrodes
104
a
and
104
d
and the on-gate insulator films
106
a
and
106
b
. The silicon oxide film is anisotropically etched thereby forming side wall insulator films
107
a
on both side surfaces of the gate electrode
104
a
. Further, side wall insulator films
107
b
are formed on both side surfaces of the gate electrode
104
d.
An n-type impurity is injected through the side wall insulator films
107
a
and
107
b
and the on-gate insulator films
106
a
and
106
b
serving as masks, thereby forming an n
+
drain region
110
a
and an n
+
source region
110
b.
Referring to
FIG. 22
, an interlayer insulator film
111
consisting of a silicon oxide film is formed on the silicon substrate
101
by CVD, to cover the side wall insulator films
107
a
and
107
b
and the on-gate insulator films
106
a
and
106
b
. A prescribed resist pattern (not shown) is formed on the interlayer insulator film
111
.
The interlayer insulator film
111
is anisotropically etched through the resist pattern serving as a mask, thereby forming the contact hole
112
b
exposing the surface of the n
+
drain region
10
a
. Further, the contact hole
112
c
is formed to expose the surface of the n
+
source region
110
b.
Referring to
FIG. 23
, a barrier metal film
113
consisting of a titanium film and a titanium nitride film is formed by sputtering, for example, to cover the side surfaces and the bottom surfaces of the contact holes
112
a
and
112
c
and the upper surface of the interlayer insulator film
111
. A tungsten film (not shown) is formed on the barrier metal film
113
by CVD, for example.
A resist pattern (not shown) is formed on the tungsten film. The tungsten film and the barrier metal film
113
are anisotropically etched through the resist pattern serving as a mask, thereby forming wiring layers
114
a
,
114
b
and
114
c
. A principal part of the memory cell of the SRAM is completed through the aforementioned steps.
In the aforementioned SRAM, however, six MOS transistors must be formed for each memory cell. As compared with another high-resistance memory cell, for example, employing no transistors as load elements, therefore, the area occupied by the memory cell is increased.
Further, the contact holes for electrical connection with the transistors must be provided for the respective transistors. Consequently, the size of the semiconductor chip may be disadvantageously increased.
When approximating the contact holes to the gate electrode or narrowing the element forming regions in order to solve these problems, however, the following problems arise:
When approximating the contact holes to the gate electrode, the surface of the gate electrode
104
a
may be exposed when the contact hole
112
c
is formed in the step shown in
FIG. 22
, for example. Therefore, tungsten embedded in the contact hole
112
c
may be shorted to the gate electrode
104
a.
When narrowing the element forming regions, the field isolation film
103
may be excessively etched when the contact hole
112
b
is formed in the step shown in
FIG. 22
, for example. Therefore, a current may leak from tungsten embedded in the contact hole
112
b
to the p well
102
through the excessively etched part of the field isolation film
103
.
Therefore, the area occupied by the memory cell is so hard to narrow that the chip size cannot be reduced.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a semiconductor device capable of performing desired operations and reducing the chip size.
A semiconductor device according to a first aspect of the present invention comprises a first conductivity type region, an element forming region, a semiconductor element, an insulator film and a first contact hole. The first conductivity type region is formed on the main surface of a semiconductor substrate. The element forming region is separated on the main surface of the semiconductor substrate by an element isolation film and formed on the surface of the first conductivity type region. The semiconductor element is formed on the element forming region. The insulator film is formed on the semiconductor substrate to cover the semiconductor element. The first contact hole is formed in the insulator film, to expose the surface of the element forming region. The semiconductor element has an electrode part, a pair of second conductivity type first impurity regions, and a second conductivity type second impurity region. The electrode part is formed across the element forming region. The pair of second conductivity type first impurity regions are formed on one side and

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