Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-26
2003-01-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C438S230000, C438S303000, C438S595000
Reexamination Certificate
active
06504192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device having a transistor, and more particularly, to a semiconductor device which has an insulating-gate-type field-effect transistor of an LDD structure with a side wall formed therein and which is allowed to have desired transistor characteristics by placing a dummy electrode to control a width of the side wall of the gate electrode, and to a manufacturing method for such a semiconductor device.
2. Description of the Prior Art
In recent years, along with increasing degree of integration in an integrated circuit, a gate length of a transistor has been shortened, and as the result of this, there occur short channel effect and hot carrier effect. Therefore, there has come to be widely used a LDD (Lightly Doped Drain) structure, that is, a structure in which impurity density at a drain diffusion region in the vicinity of the gate electrode is lowered as compared with the impurity density at the other regions.
Not only in the MOS-type transistors, but also in semiconductor devices (multi-input-gate type MIS devices) formed by placing a plurality of gate electrodes on the same substrate in parallel with each other and connecting a plurality of MIS transistors in series with each other, the above-mentioned LDD structure has come to be applied to each of the MIS transistors.
Conventionally, with respect to the semiconductor device having an insulating-gate-type field-effect transistor (hereinafter, referred to as MISFET), in the case where a film facing a side face of the gate electrode is formed by dry etching such as an RIE method, that is, a side wall spacer is formed, as indicated by its cross-section shown in
FIG. 14
, since reaction products at the time of etching are allowed to deposit more thickly at positions having greater gaps between the gate electrodes
2
, the width of the side wall spacer
3
a
is widened. On the other hand, as illustrated in
FIG. 15
, at positions where the gaps between the gate electrodes
2
are dense, since the deposition of the reaction products is small, the width of the side wall spacer
3
a′
becomes narrower. Consequently, differences (deviations) occur in the width of the side wall spacer
3
a
due to differences in the density of the gaps between the gate electrodes.
In the present invention, this deviation characteristic at the time of formation of the side wall is referred to as “etching characteristic in the side wall width”, or simply referred to as “etching characteristic”. In particular, in the case of the transistor using the LDD structure, the occurrence of deviations in the width of the side wall spacer
3
a
causes a difference in the source-drain structure, resulting in a difference in the transistor characteristics and there arise subsequent deviations in the characteristics. In the transistor using the LDD structure, the setting of the width of the side wall spacer is one of essential factors for determining the transistor characteristics. The present invention has been devised to solve the above-mentioned problem, and its objective is to realize a semiconductor device which can provide desired transistor characteristics by controlling the width of the side wall spacer, and also to provide a semiconductor device which becomes free from deviations in the transistor characteristics by eliminating deviations in the width of the side wall spacer due to differences in the density of the layout gaps between the gate electrodes.
As described above, the present invention provides a structure of a semiconductor device and a manufacturing method thereof, where the width of the side wall spacer is controlled or properly adjusted so as to eliminate deviations occurring in the transistor characteristics or to effectively utilize the difference occurring in the transistor characteristics to obtain desired transistor characteristics.
SUMMARY OF THE INVENTION
In order to achieve the above-mentioned objectives, the present invention adjusts differences in density of layout gaps between gate electrodes by properly arranging a dummy electrode so that a width of a side wall spacer is controlled and transistor characteristics are adjusted.
According to a first aspect of the present invention, a semiconductor device which has a transistor having a side wall spacer formed, comprises: a gate array in which a gap between a desired gate electrode and an adjacent electrode is adjusted in difference; wherein a width of the side wall spacer is controlled by adjusting the gap in difference while an effective channel length of the transistor is maintained constant, whereby characteristics of the transistor are adjusted.
In this construction, the gap difference between gate electrodes is adjusted by providing a dummy electrode in the vicinity of the desired gate electrode or by an arrangement of having no dummy electrode provided in the vicinity of the desired gate electrode.
The gap difference between gate electrodes may be eliminated by providing a dummy electrode in the vicinity of the desired gate electrode, thereby obtaining a constant width of the side wall spacer.
The gap difference between gate electrodes may be changed by providing a dummy electrode in the vicinity of the desired gate electrode, thereby changing the width of the side wall spacer.
In accordance with the above-mentioned arrangement, by eliminating differences in density of providing the gate electrodes, the same width of the side wall spacer can be obtained, and it is possible to provide a semiconductor device having uniform transistor characteristics.
According to a second aspect of the present invention, a method of manufacturing a semiconductor device having a transistor formed with a side wall spacer, comprises the steps of: carrying out a patterning process by dry etching using a photoresist mask to form gate electrodes on a substrate; stacking a silicon dioxide insulating film covering upper face and side faces of each gate electrode to coat an entire exposed surface on the substrate; and forming a side wall spacer of each gate electrode by dry etching, wherein a gap between the gate electrodes is adjusted in difference so that a width of the side wall spacer is controlled due to etching characteristics during the formation of the side wall spacer.
In this method, an effective channel length of the transistor is defined by a space distance between low-density impurity regions thereof that have been formed by injection prior to the formation of the side wall spacer, and the width of the side wall spacer is controlled while maintaining constant.
In the arrangement and method of the present invention make, it possible to realize a structure of a semiconductor device and a manufacturing method thereof which can adjust the distance in which a dummy electrode is arranged so that it becomes possible to control the width of the side wall spacer, and consequently to provide desired transistor characteristics.
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patent: 5863824 (1999-01-01), Gardner et al.
patent: 6133132 (2000-10-01), Toprac et al.
patent: 6232189 (2001-05-01), Yi et al.
patent: 6409879 (2002-06-01), Toprac et al.
patent: 8-32058 (1996-02-01), None
patent: 10-12881 (1998-01-01), None
Huynh Andy
McDermott & Will & Emery
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