Semiconductor device

Details Semiconductor device Semiconductor device

2001-03-16

2003-05-20

Niebling, John F. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Including semiconductor material other than silicon or...

Containing germanium, ge

C257S316000, C257S321000, C257S348000

Reexamination Certificate

active

06566734

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same. In particular, the present invention relates to a method of producing a field effect transistor with stable electrical characteristics, and to a semiconductor device obtained by the production method.
2. Description of the Background Art
One example of a method of producing a conventional field effect transistor will be described with reference to “FUNDAMENTALS OF MODERN VLSI DEVICES”, ed. YUAN TAUR et al., Cambridge University Press. With reference to
FIG. 45
, a p-type well
102
and an element isolation film
103
, for example, are formed in a silicon substrate
101
. Next, a pad oxide film
104
is formed on the silicon substrate
101
. Next, a p-type impurity is ion-implanted to form a channel impurity region
116
. Thereafter, the pad oxide film
104
is removed.
Next, a polysilicon film (not illustrated) is formed through the intermediary of a silicon oxide film on the silicon substrate
101
. A predetermined photoresist pattern (not illustrated) is formed on the polysilicon film. With the use of the photoresist pattern as a mask, the polysilicon film and the silicon oxide film are subjected to anisotropic etching to form a gate insulation film
117
and a gate electrode
118
referring to FIG.
46
. With the use of the gate electrode
118
as a mask, an n-type impurity is ion-implanted to form a pair of extension regions
109
a
,
109
b.
Next, a silicon oxide film (not illustrated) is formed on the silicon substrate
101
so as to cover the gate electrode
118
. The entire surface of the silicon oxide film is subjected to anisotropic etching to form side wall silicon oxide films
110
on both side surfaces of the gate electrode
118
, as shown in FIG.
47
.
Next, referring to
FIG. 48
, an n-type impurity is ion-implanted with the use of the gate electrode
118
and the side wall silicon oxide film
110
as a mask so as to form a pair of source/drain regions
111
a
,
111
b.
Next, referring to
FIG. 49
, cobalt silicide films
112
a
,
112
b
,
112
c
are formed in a sell-aligned manner on the surface of the pair of exposed source/drain regions
111
a
,
111
b
and the gate electrode
118
. Thereafter, referring to
FIG. 50
, a silicon oxide film
113
is formed on the silicon substrate
101
.
Thus, referring to,
FIGS. 51 and 52
, a field effect transistor including the gate electrode
118
, the extension regions
109
a
,
109
b
, and the source/drain regions
111
a
,
111
b
is formed on an element formation region partitioned by the element isolation film
103
. Here,
FIG. 51
illustrates a cross-sectional structure in the gate length direction, and
FIG. 52
illustrates a cross-sectional structure in the gate width direction.
However, the conventional method of producing a semiconductor device involves the following problems.
The first one of the problems is a problem accompanying the turn-around, i.e., diffusion of impurities into the extension regions
109
a
,
109
b
to a region immediately under the gate electrode
118
, reversion conductivity type. Referring to
FIG. 46
, the pair of extension regions
109
a
,
109
b
are formed on the surface of the silicon substrate
101
with the use of the gate electrode
118
as a mask. At this time, the ions serving as the impurity may possibly be implanted to turn around to a region under the gate electrode
118
.
Further, referring to
FIGS. 53 and 54
, by a heat treatment in a process after the, extension regions
109
a
,
109
b
are formed, the impurity of the extension regions
109
a
,
109
b
is diffused to a region under the gate electrode
118
, so that the extension regions
109
a
,
109
b
are both extended to the region under the gate electrode
118
.
By turn-around (diffusion) of the extension regions
109
a
,
109
b
to the region immediately under the gate electrode
118
, the effective gate length (a) of the field effect transistor will be shorter. When the gate length becomes less than about 100 nm in accordance with the miniaturization of semiconductor devices, the turn-around of about 10 nm of the extension regions
109
a
,
109
b
will be a problem, and the short channel effect deteriorates the electrical characteristics in the field effect transistor, such as increase in the subthreshold current.
Furthermore, referring to
FIGS. 53 and 54
, the part of the extension regions
109
a
,
109
b
formed immediately under the gate electrode
118
and having a comparatively low impurity concentration has a higher electric resistance than the part of the extension regions
109
a
,
109
b
located immediately under the side wall dielectric film.
For this reason, the obtained field effect transistor will be equivalent to a field effect transistor in which resistances R are connected in series to the source and the drain, referring to FIG.
55
. This makes it hard for the electric current to flow, raising problems such as a slow operation speed.
Next, the second one of the problems is a problem accompanying the rise of impurity concentration in the surface of the channel impurity region
116
. In order to meet the miniaturization of field effect transistors, the impurity concentration of the channel impurity region
116
must be raised. The channel impurity region
116
is formed in a step shown in
FIG. 45
, and the impurity of the channel impurity region
116
will be diffused by a heat treatment in a later-performed process.
In particular, the impurity that diffuses towards the surface of the silicon substrate
101
raises the surface concentration of the channel impurity region
116
. Higher surface concentration of the channel impurity region
116
causes rise of the threshold voltage in the field effect transistor.
On the other hand, the semiconductor devices are now designed to have a lower power supply voltage, such as from 5V to 3.3V. In order to meet such a lower power supply voltage, the threshold voltage of the field effect transistor is preferably lower. For this reason, the rise in the threshold voltage of the field effect transistor is against this demand.
Next, the third one of the problems is a problem accompanying the electric field concentration at an end of the element isolation film
103
. In order to meet the miniaturization of semiconductor devices, a trench isolation method is employed as an element isolation film
103
for electrically isolating a field effect transistor from other field effect transistors. In the case of an element isolation film
103
formed by the trench isolation method, the electric field of the gate electrode
118
in the neighborhood of the element isolation film
13
is more concentrated than the electric field in the other parts, as shown by B in FIG.
57
. By concentration of electric field, a parasitic transistor having a lower threshold voltage is formed in the neighborhood of the element isolation film
103
.
In other words, the obtained field effect transistor will be equivalent to a transistor in which the intended transistor T
1
is connected in parallel to a parasitic transistor T
2
, as shown in FIG.
58
. Therefore, this parasitic transistor T
2
causes the electric current to flow at a lower gate voltage to generate a superfluous leakage current.
SUMMARY OF THE INVENTION
Thus, one object of the present invention is to provide a method of producing a semiconductor device that eliminates the aforesaid problems of the prior art and the other object is to provide a semiconductor device obtained by such a production method.
A method of producing a semiconductor device according to one aspect of the present invention is a method of producing a semiconductor device including an impurity region forming step of forming a pair of impurity regions of first conductivity type on a surface of a semiconductor substrate to sandwich a region that is to become a channel region, and an electrode forming step of forming a gate electrode on the region that is to become the channel region, wherein the method includes a removi

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