Semiconductor device

Details Semiconductor device Semiconductor device

2001-05-04

2003-03-04

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000

Reexamination Certificate

active

06529039

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device preferable for realizing a large-scale function system on a single chip and in particular, to a semiconductor device having terminals of an identical function at a plurality of sides of a macro cell, so that these terminals can selectively be used.
2. Description of the Related Art
It is known to combine logic properties whose operations have been verified, so as to constitute a functional system on a single chip. For example, by arranging (layout) macro cells such as an MPU and a DSP and various macro cells such as a memory and various I/O interfaces on a chip and connecting the macro cells by wiring, it is possible to realize a so-called system LSI having various functions dedicated to a particular use.
FIG. 15
shows a configuration of a macro cell designed for a single chip and used as a single chip. In
FIG. 15
, a reference symbol
100
denotes a chip (single chip),
101
to
164
denote pads (external electrodes), and
200
denotes a macro cell formed on the chip. The pads
101
to
104
are located at positions considering the pin arrangement of a package (containing a semiconductor chip) (not depicted). Here is given an example in which a first output pad
101
is arranged at the left side of the chip
100
, a second output pad
102
is arranged at the lower side a third output pad
103
is arranged at the right side, and an input pad
104
is arranged at the upper side.
The macro cell
200
includes: an internal kernel circuit block
300
performing a predetermined functional operations; three output buffers
210
,
220
, and
230
; an input buffer
240
; three output terminals
201
,
202
, and
203
; and an input terminal
204
. The internal kernel circuit block
300
has a circuit portion (not depicted) performing a predetermined functional operation according to an input signal and terminals
301
to
304
.
The terminals
201
to
204
for connecting the macro cells are designed considering the arrangement of the pads
101
to
104
. The input terminal
204
is arranged at the upper side of the macro cell
200
and the output terminals
201
,
202
, and
203
are arranged at.the left side, the lower side, and the right side, respectively. The pads
101
to
104
are connected to the terminals
201
to
204
of the macro cell
200
by the macro external wires
111
to
114
. The terminal arrangement of the internal kernel circuit block
300
is designed considering the arrangement of the terminals (for connecting the macro cells) of the macro cell
200
. An input terminal
304
is arranged at the upper side of the internal kernel circuit block
300
, and a first, a second, and a third output terminal
301
,
302
, and
303
are arranged at the left side, at the lower side, and at the right side of the internal kernel circuit block
300
.
An input buffer
240
is arranged between the input terminal
204
of the macro cell
200
and the input terminal
304
of the internal kernel circuit block
300
, and the input terminal
204
of the macro cell
200
is connected to the input terminal of the input buffer
240
by an in-macro wire while the output terminal of the input buffer
240
is connected to the input terminal
304
of the internal kernel circuit block
300
by an in-macro wire. A first output buffer
210
is arranged between the first output terminal
301
of the internal kernel circuit block
300
and the first output terminal
201
of the macro cell
200
, and the first output terminal
301
of the internal kernel circuit block
300
is connected to the input terminal of the first output buffer
210
by an in-macro wire while the output terminal of the first output buffer
210
is connected to the first output terminal
201
of the macro cell
200
by an in-macro wire. Similarly, via the second and the third output buffers
220
and
230
, the output terminals
302
and
303
of the internal kernel circuit block
300
are connected to the output terminals
202
and
203
of the macro cell.
In
FIG. 15
, the respective terminals are located so as to minimize the wires outside and inside the macro cell. This reduces a signal transfer delay caused by wiring, thereby enabling to obtain a high-speed operation.
FIG. 16
shows a combination of a macro chip designed for a single chip and a macro chip designed for a logic core.
FIG. 16
shows.a configuration example having the macro cell
200
(designed for a single chip) shown in
FIG. 15
arranged together with another macro cell (designed for the IP) located below the macro cell
200
. The macro cell
400
includes input terminals W, X, and Y via which output signals of the macro cell
200
are fed, and an output terminal Z for outputting a signal (input signal to the macro cell
200
) supplied to the macro
200
. Here, the terminals W, X, Y and Z are arranged at the upper side of the macro cell
400
.
When the macro cell
200
designed as a single chip is used as it is in combination with the macro cell
400
for the logic arranged below the macro cell
200
, a macro-connecting wire
501
between the first output terminal
201
and the first input terminal W needs to be quite long. When the wire becomes longer, the wire capacity is increased, causing a delay in signal transfer. To cope with this, a buffer
510
is arranged in the route of the macro-connecting wire
501
, so as to reduce the signal transfer delay. A macro-connecting wire
502
between the second output terminal
201
and the second input terminal X is short, and they are connected to each other directly without providing a buffer. A macro-connecting wire
503
between the third output terminal
203
and the second input terminal Y is long, and they are connected to each other via a buffer. A macro-connecting wire
504
between the output terminal Z and the input terminal
204
is further longer, and they are connected to each other via two buffers arranged at a certain interval.
FIG. 17
shows a configuration example of using a macro cell designed for the logic core in combination with another macro cell designed for the logic core. The macro cell
600
shown in
FIG. 17
is identical to the internal kernel circuit block
300
shown in FIG.
15
and FIG.
16
and has a functional operation identical to that of the macro cell
200
shown in FIG.
15
and FIG.
16
. In this macro cell
600
, the terminals W, X, Y, and Z are arranged at the lower side considering a connection with the other macro cell
400
arranged below. Since locations of the terminals W, X, Y, and Z are changed, the location of the input buffer
240
and the in-macro wiring are different from the macro cell
200
shown in FIG.
15
and FIG.
16
. By using the macro cell
600
having such a terminal arrangement, it is possible to reduce the macro-connecting wires
511
to
514
.
FIG. 18
shows a configuration example for realizing a single chip by using a macro cell designed for the logic core. When utilizing the macro cell (designed for the logic core)
600
shown in
FIG. 17
to constitute a chip having the pad arrangement shown in
FIG. 15
, it is necessary to use long wires between the terminals w, y, z arranged at the lower side of the macro cell
600
and the pads
101
,
103
, and
104
. To cope with this, an output buffer
710
is arranged in the wire between the terminal w and the pad
101
, and an output buffer
720
is arranged in the wire between the terminal y and the pad
103
. Furthermore, in the wire between the pad
104
and the terminal z, there are arranged input buffers
730
and
740
at a certain interval. This reduces the delay in signal transfer caused by increase of the wire capacity.
Japanese Patent Publication 6-140566 discloses a semiconductor integrated circuit having a plurality of mega macro cells having terminals connected to one another by macro external wires, wherein identical terminals are arranged at the four sides of the mega macro cell and are electrically connected to one another, thereby improving the wiring efficiency. Since id

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