Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-12
2003-04-08
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S064000, C257S066000
Reexamination Certificate
active
06545328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device including a gate electrode or source/drain regions obtained by control of diffusion and activation of impurities in polycrystalline semiconductor film, and a method for fabricating the same.
2. Description of the Related Art
Recently, CMOS transistors having a dual-gate structure have been developed. The dual-gate structure is provided to prevent variation of the threshold voltage of a transistor as well as the short channel effect. This structure includes two surface-channel transistors, one of which is an NMOS transistor having a gate electrode containing an n-type impurity and the other of which is a PMOS transistor having a gate electrode containing a P-type impurity.
Japanese Laid-Open Publication No. 6-224380 discloses a method for doping a gate electrode of a conventional dual-gate structure CMOS transistor with an impurity and activating the impurity in the doped gate electrode.- Specifically, as shown in
FIG. 1
, a p
−
-well
106
, an n
−
-well
107
, a field oxide film (element-isolating region)
102
, and an inversion prevention layer
104
are provided on a semiconductor substrate
101
in a well-known way. A gate insulation film
105
(e.g., made of oxide film) is provided to cover those layers in a well-known way. A polycrystalline silicon film
103
to serve as a gate electrode is formed on the gate insulation film
105
with LPCVD. Thereafter, the polycrystalline silicon film
103
is patterned into the desired shape, and the source/drain regions and the gate electrode are doped with an impurity as a dopant by means of ion implantation. The resulting structure is then subjected to thermal treatment so as to activate the implanted dopant ions.
Japanese Laid-Open Publication No. 3-138930 discloses a transistor including a shallow junction which is provided in source/drain regions using a stacking structure for preventing the short channel effect which emerges as the transistor becomes smaller.
FIG. 2
is a cross-sectional view showing diagrammatically a structure of the stacking-structure transistor disclosed the above-described publication.
In the conventional transistor having a structure as shown in
FIG. 2
, a gate electrode structure includes a gate insulating film
203
, a gate electrode
204
, and an insulating top layer
205
. The gate electrode structure is provided over a region which will be a channel region between regions which will be source/drain regions
207
. The gate electrode structure and those regions are positioned between field oxide films
202
(element-isolating regions) provided on a substrate
201
. Sidewalls
211
are provided on the sides of the gate structure.
To form the source/drain regions
207
in this structure, a polycrystalline silicon film is provided to cover the gate electrode structure. Thereafter, the polycrystalline silicon film is etched back to a level indicated reference numeral
206
shown in FIG.
2
. The polycrystalline silicon film
206
is doped with an impurity as a dopant and subjected to thermal treatment. The thermal treatment causes a solid phase diffusion so that the dopant diffuses from the polycrystalline silicon film
206
into the semiconductor substrate
201
, thereby producing the source/drain regions
207
.
After the formation of the source/drain regions
207
, a silicide film
208
and an inactive dielectric layer
209
are formed over the polycrystalline silicon film
206
, and a metal wire
210
is provided, resulting in the structure shown in FIG.
2
.
However, when attempting to fabricate the conventional dual-gate-structure CMOS transistor using the surface-channel transistor, the following problems arise.
Phosphorous and arsenic as n-type impurities have a lower diffusion rate and a lower activation ratio in the polycrystalline silicon than Boron as a p-type impurity. For this reason, carriers are adversely depleted from the gate insulating film side of the gate electrode. The depletion layer of the gate electrode has a capacitance which is added in series to the capacitance of the gate insulating film, resulting in a reduction in effective capacitance. This reduces a driving current for the transistor. The driving current varies depending on the degree of depletion.
In general, impurity implantation is simultaneously carried out both for the gate electrode and the source/drain regions to be formed in order to reduce the number of steps in formation of the dual-gate-structure CMOS transistor. In this case, preferably, the source/drain function has a shallow junction so as to prevent the short channel effect of the transistor. To this end, reduced energy of ion implantation is preferable. This is, however, likely to deplete carriers from the gate electrode.
As described above, there is a trade-off between prevention of depletion in the gate electrode and prevention of the short channel effect. The prevention of the short channel effect leads to the depletion in the gate electrode. On the other hand, when the gate electrode is doped under conditions for preventing the depletion, the junction in the source/drain regions become deep, resulting in an increase in the short channel effect.
On the other hand, the short channel effect is increased as the size of the transistor is decreased. To prevent the short channel effect in this situation, the stacking-structure transistor has a shallow junction which is formed in the source/drain region using the stacking structure. When the source/drain regions are provided with the stacking structure using polycrystalline silicon film, the following problems arise.
To form as shallow a junction as possible, the amount of impurities implanted into the polycrystalline silicon film is preferably reduced so as to avoid the influence of extraordinary accelerated diffusion from a high-concentration region. The reduced amount of impurities of the source/drain regions does not cause the source/drain regions to have a sufficiently lowered level of resistance, resulting in an increase in parasitic resistance. This leads to a decrease in a transistor current in operation.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method for fabricating a semiconductor device including a polycrystalline semiconductor film containing impurities, includes the steps of introducing the impurities into the polycrystalline semiconductor film; and subjecting the polycrystalline semiconductor film to thermal treatment in an oxidization atmosphere to carry out oxidization of the polycrystalline semiconductor film and activation of the impurities simultaneously.
According to another aspect of the present invention, a method for fabricating a semiconductor device including a polycrystalline semiconductor film containing impurities, includes the steps of depositing the polycrystalline semiconductor film; oxidizing the polycrystalline semiconductor film; introducing the impurities into the oxidized polycrystalline semiconductor film; and subjecting the oxidized polycrystalline semiconductor film to annealing to activating the impurities.
In one embodiment of this invention, the method for fabricating a semiconductor device includes the steps of: depositing an amorphous silicon film; and obtaining the polycrystalline silicon film by crystallizing the amorphous silicon film.
In one embodiment of this invention, the polycrystalline semiconductor film has a crystal defect density of about 1×10
18
cm
−3
or less.
In one embodiment of this invention, the polycrystalline semiconductor film is a polycrystalline silicon film.
In one embodiment of this invention, the impurities are phosphorous, boron, arsenic, or antimony.
According to another aspect of the present invention, a semiconductor device includes an insulating-gate field effect transistor structure having a gate electrode. The gate electrode includes a polycrystalline semiconductor film having a
Iwata Hiroshi
Morosawa Narihiro
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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