Semiconductor device

Details Semiconductor device Semiconductor device

2001-08-29

2002-11-05

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S210000, C257S750000

Reexamination Certificate

active

06476493

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to gate arrays generally.
BACKGROUND OF THE INVENTION
Various types of gate arrays are well known in the art. Gate arrays comprise a multiplicity of transistors which are prefabricated. A specific application is achieved by customizing interconnections between the transistors.
Routing arrangements have been proposed for reducing the number of custom masks and the time needed to manufacture gate arrays by prefabricating some of the interconnection layers in two-metal layer gate array devices. Prior art devices of this type typically employ three custom masks, one each for the first metal layer, via layer and second metal layer.
U.S. Pat. No. 4,197,555 to Uehara describes a two-metal layer gate array device wherein the first and second metal layers are pre-fabricated and the via layer is customized. Uehara also shows use of pre-fabricated first metal and via layers and customization of the second metal layer.
U.S. Pat. Nos. 4,933,738; 5,260,597 and 5,049,969 describe a gate array which is customized by forming links in one or two prefabricated metal layers of a two-metal layer device.
U.S. Pat. No. 5,404,033 shows customization of a second metal layer of a two-metal layer device.
U.S. Pat. No. 5,581,098 describes a gate array routing structure for a two-metal layer device wherein only the via layer and the second metal layer is customized by the use of a mask.
SUMMARY OF THE INVENTION
The present invention seeks to provide a multiple layer interconnection structure for a gate array device which has significant advantages over prior art structures.
The present invention employs at least three metal interconnection layers Customization is preferably realized by customization of a via layer and a layer overlying that via layer.
There is thus provided in accordance with a preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band including a multiplicity of second metal layer strips extending perpendicular to the first axis, and at least one via connecting at least one second metal layer strip with the first metal layer underlying the second metal layer.
Preferably the at least one via includes a repeating pattern of vias.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer underlying the second metal layer includes a multiplicity of first metal layer strips extending generally parallel to the multiplicity of second metal layer strips. Furthermore, at least one of the first metal layer strips is electrically connected at ends thereof to different second metal layer strips for providing electrical connection therebetween.
Further in accordance with a preferred embodiment of the present invention the second metal layer strips include both relatively long strips and relatively short strips, at least one of the relatively short strips being connected to the first metal layer by a via. Preferably the relatively short second metal layer strips are arranged in side by side arrangement. Alternatively the relatively short second metal layer strips are arranged in spaced coaxial arrangement.
Additionally or alternatively the third metal layer includes a bridge connecting adjacent pairs of said relatively short second metal layer strips.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending perpendicular to the second metal layer strips and being connected thereto by a via. Furthermore, the third metal layer includes at least one third metal layer strip extending parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer comprises at least one first metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Preferably the third metal layer includes at least one third metal layer strip extending perpendicular to the second metal layer strips and being connected thereto by a via.
Moreover in accordance with a preferred embodiment of the present invention the first metal layer includes first metal layer strips extending generally perpendicular to the second metal layer strips, the first metal layer strips being electrically connected at ends thereof by said vias to the second relatively short metal layer strips.
Still further in accordance with a preferred embodiment of the present invention the third metal layer comprises at least one third metal layer strip extending parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention also including at least one third metal layer strip extending parallel to the second metal layer strip and connecting two coaxial second metal layer strips.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a multiplicity of second metal layer strips extending perpendicular to the first axis, adjacent ones of the second metal layer strips having ends which do not lie in a single line.
Further in accordance with a preferred embodiment of the present invention the second metal layer strips are interlaced with one another.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strip and being connected thereto by a via.
Additionally in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.
There is provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to the first axis, and a plurality of mutually parallel relatively short second metal layer strips extending generally parallel to the first axis.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Preferably at least one of the third metal strips connects two second metal layer strips by means of vias.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias. Preferably at least one of the third metal strips connects two second metal layer strips by means of vias.
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