Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
1999-05-25
2002-11-12
Frech, Karl D. (Department: 2876)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S093000, C365S233100, C365S230060
Reexamination Certificate
active
06480033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a semiconductor device having a circuit such as a command decoder that has the function of decoding command signals, which represent various kinds of commands, synchronously with an internal clock, and judging the states of the command signals.
In such a command decoder or the like, normally, states or patterns of various command signals are judged in order to produce a command judgment signal synchronous with an internal clock (normally referred to as a clocked judgment signal). The command judgment signals are output through command pins of an output port.
In recent years, dynamic random access memory (hereinafter abbreviated to DRAM) that is a semiconductor integrated circuit having a semiconductor device, which includes the command decoder or the like incorporated therein, has been required to exhibit a high processing speed.
However, for suppressing multi-signal selection, that is simultaneous selection of two or more than two clocked judgment signals to be output through command pins, the high processing speed exhibited by the SDRAM must be sacrificed. Otherwise, it becomes necessary to fully suppress a skew equivalent to a dispersion in timing between different command signals. The present invention relates to a means for coping with the multi-signal selection of clocked judgment signals and the skew between command signals while meeting the request for a higher processing speed to be exhibited by the DRAM.
2. Description of the Related Art
Normally, data is input as an external input signal to the DRAM. The input data is processed according to a clocked judgment signal produced by judging the states or patterns of command signals. Consequently, desired data is output. Especially, novel DRAMs including a synchronous DRAM (usually abbreviated to SDRAM) capable of transferring data at a high speed is designed to provide a data transfer speed corresponding to a frequency of, for example, 100 MHz or higher than 100 MHz. At this time, input or output of data and judgment of the states of the command signals must be carried out at a predetermined accurate phase relative to an externally supplied high-speed external clock. In other words, as far as the SDRAM is concerned, according to what timing a clocked judgment signal is output through a command pin of a command decoder or the like is important for outputting desired data quickly and stably.
Now, for a better understanding of problems on semiconductor integrated circuits including conventional semiconductor devices having the function of judging the states of command signals, the configuration and operations of conventional semiconductor devices will be described later with reference to
FIG. 1
to
FIG. 4
mentioned in “BRIEF DESCRIPTION OF THE DRAWINGS.”
A circuit block diagram showing the outline configuration of a first example of conventional semiconductor devices having the function of judging the states of command signals, is illustrated in
FIG. 1. A
conventional semiconductor device of the first example shown in
FIG. 1
has a first current mirror circuit
310
, a second current mirror circuit
320
, and a third current mirror circuit
330
. The first current mirror circuit
310
, second current mirror circuit
320
, and third current mirror circuit
330
amplify various command signals input through external control pins and thus determine the output levels of the command signals. The various command signals are, for example, a row address strobe /RAS, a column address strobe /CAS, and a write enabling signal /WE. Herein, the first to third current mirror circuits amplify the row address strobe /RAS, column address strobe /CAS, and write enabling signal /WE, thus producing command determination signals rasz, casz, and wez. The command determination signals rasz, casz, and wez are high (“H”: high voltage) or low (“L”: low voltage).
In
FIG. 1
, there are shown a first latch circuit
410
, second latch circuit
420
, and third latch circuit
430
for holding the command determination signals rasz, casz, and wez sent from the first to third current mirror circuits. The first to third latch circuits are each realized with a set-reset flip-flop (normally abbreviated to SFF). The first to third latch circuits latch information of command signals (that is, the command determination signals rasz, casz, and wez) synchronously with a clock (that is, an internal clock clkz). The clock is input via a current mirror circuit
500
for a clock through an external clock (CLK) input clock pin. The first to third latch circuits output command information latch signals rascz, cascz, and wecz that are in phase with the input command determination signals. The first to third latch circuits also output command information latch signals rascx, cascx, and wecx that are out of phase with the command determination signals. The current mirror circuit
500
for a clock functions as an input buffer for converting the level of the external clock CLK so as to produce an internal clock clkz.
Furthermore, in
FIG. 1
, there is shown a command decoder
100
for decoding the command information latch signals output from the first to third latch circuits. The command decoder
100
judges the states of the command signals including the row address strobe /RAS, column address strobe /CAS, and write enabling signal /WE. The command decoder
100
judges the states of the command signals from command information signals latched synchronously with the internal clock clkz by the first to third latch circuits. The states of the command signals indicate an operation to be performed by the SDRAM or the like. Moreover, the results of judgment made on the states of the command signals by the command decoder
100
are reported in the form of a “H” level (high-level) or “L” level (low-level) clocked judgment signal via an inverter through an associated node. The “H” level or “L” level clocked judgment signal is, for example, a clocked judgment signal AZ or BZ. The inverter is, for example, inverters
110
and
120
. The node is, for example, a node n
01
or n
11
.
The practical circuitry of the current mirror circuits, latch circuits, and command decoder will be described later in “DESCRIPTION OF THE PREFERRED EMBODIMENTS.”
Referring to
FIG. 2
, the actions of a conventional semiconductor device of a second example of conventional semiconductor devices including the current mirror circuits, latch circuits, and command decoder will be clarified below.
FIG. 2
shows the waveforms of input and output signals of components of the current mirror circuits, latch circuits, and command decoder. However, for brevity's sake, the waveforms of the input and output signals of the first current mirror circuit
310
and second current mirror circuit
320
will be shown as representatives of those of the input and output signals of the plurality of current mirror circuits. Likewise, the waveforms of the input and output signals of the first latch circuit
410
and second latch circuit
420
will be shown as representatives of those of the input and output signals of the plurality of latch circuits.
Referring to
FIG. 2
, signals (the command determination signals rasz and casz in
FIG. 2
) are transmitted to the output stages of the first and second current mirror circuits
310
and
320
. The signals are synchronous with and in phase with the row address strobe /RAS and column address strobe /CAS input through the external control pins. The internal clock clkz in phase with the clock CLK (that is, the external clock) input through the clock pin is transmitted to the output stage of the current mirror circuit
500
for a clock. In this case, the command determination signals rasz and casz and the internal clock clkz make a transition from “L” level to “H” level or a transition from “H” level to “L” level substantially simultaneously.
Data items (the command determination signals rasz and casz) output from the first and second current mirro
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