Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-05-29
2002-12-03
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S207000, C257S211000, C257S503000, C257S758000, C257S774000
Reexamination Certificate
active
06489689
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having pads. More particularly, the present invention relates to a semiconductor device in which a global step between an I/O region along the periphery of a chip and a central region of the chip is reduced even when the width of a metal line connected to a pad is increased.
In recent years, the degree of integration of a semiconductor integrated circuit has been increasing along with the advancement of minute processing techniques. A multilayer wiring structure is typically employed in an integrated circuit that is fabricated with a 0.25 &mgr;m, or subsequent, design rule. Along with the miniaturization of devices, the thickness of each wiring film and interlayer insulating film in the multilayer wiring structure has been reduced. The reduction in the thickness of each wiring film also reduces the acceptable current density thereof.
A semiconductor integrated circuit typically includes I/O cells arranged along the periphery of the chip. An I/O cell includes a protection circuit for protecting the integrated circuit from an electrostatic discharge (ESD) and an input/output circuit. The width of each I/O cell has been reduced along with a reduction in the pad pitch due to an increase in the number of pins provided in an integrated circuit. Under such circumstances, for example, the acceptable current capacity of a metal line connected to the pad of an I/O cell, through which a large current is expected to flow, is increased by increasing the width thereof as much as possible, or providing the metal line in multiple layers, so as to increase the reliability thereof against possible wire breaking due to a current flow therethrough.
FIG. 8
illustrates a layout of a conventional semiconductor integrated circuit. More specifically,
FIG. 8
illustrates an I/O cell having a three-layer wiring structure. The I/O cell includes ESD protection elements, output transistors, power supply lines and a pad. The output transistors all have the same structure, and also function as the ESD protection elements. Therefore, the term “output transistors” as used herein refers to both output transistors and ESD protection elements.
FIG. 9
is a cross-sectional view taken along line
101
of
FIG. 8
, and
FIG. 10
is a circuit diagram illustrating the semiconductor integrated circuit of
FIG. 8. A
gate insulating film and an interlayer insulating film for providing an insulation between wiring layers are not shown in FIG.
8
and FIG.
9
.
In FIG.
8
and
FIG. 9
,
102
denotes a p-type semiconductor substrate, and
103
and
104
respectively denote a p-type well and an n-type well, which are provided on the semiconductor substrate
102
. Two NMOS transistors N
101
are provided on the p-type well
103
, and two PMOS transistors P
101
are provided on the n-type well
104
. The transistors N
101
and P
101
function as output transistors, and are separated from each other by a device separation region
105
. In FIG.
8
and
FIG. 9
,
106
and
107
denote n-type diffusion regions, which respectively serve as the drain and the source of the NMOS transistors N
101
, and
108
and
109
denote p-type diffusion regions, which respectively serve as the drain and the source of the PMOS transistors P
101
.
Moreover, in FIG.
8
and
FIG. 9
, VSS denotes a power supply line at a ground potential which is provided in the second wiring layer, and VDD denotes a power supply line at a predetermined potential which is also provided in the second wiring layer. The power supply line VSS is connected to the n-type diffusion region
107
, serving as the source of the NMOS transistors N
101
, via a via hole
110
, an isolated wiring region
111
which is provided in the first wiring layer, and a via hole
112
(note that the two via holes
110
and
112
appear to be a single hole in
FIG. 8
because they overlap each other in the vertical direction). The power supply line VDD is connected to the p-type diffusion region
109
, serving as the source of the PMOS transistors P
101
, via a via hole
113
, an isolated wiring region
114
which is provided in the first wiring layer, and a via hole
115
(note that the two via holes
113
and
115
appear to be a single hole in
FIG. 8
because they overlap each other in the vertical direction).
Moreover,
122
denotes a pad, and
116
denotes a metal line having a large width which is provided in the first wiring layer. The metal line
116
is used to connect the output transistors N
101
and P
101
to the pad
122
. The metal line
116
is connected to the n-type diffusion region
106
, serving as the drain of the NMOS transistors N
101
, via a via hole
117
, and to the p-type diffusion region
108
, serving as the drain of the PMOS transistors P
101
, via a via hole
118
. Furthermore, the metal line
116
is connected to the pad
122
via a via hole
119
, an isolated wiring region
120
which is provided in the second wiring layer, and a via hole
121
(note that the two via holes
119
and
121
appear to be a single hole in
FIG. 8
because they overlap each other in the vertical direction).
However, with the conventional I/O cell illustrated in FIG.
8
and
FIG. 9
, when the width of the metal line
116
is increased in order to increase the acceptable current capacity thereof, the parasitic capacitance between the metal line
116
in the first wiring layer and the power supply lines VSS and VDD in the second wiring layer may increase, thereby also increasing the delay time.
Moreover, when the width of the metal line
116
in the first wiring layer is increased in an I/O region along the periphery of the chip, the wiring area ratio of the first wiring layer in the I/O region (i.e., the ratio of the total area of wiring within a unit area, e.g., 100 &mgr;m×100 &mgr;m, with respect to the unit area) increases with respect to the wiring area ratio of the first wiring layer in the central region of the chip. The difference between the wiring area ratio of the first wiring layer in the I/O region and that in the central region of the chip may cause a physical step or unevenness (hereinafter, referred to simply as a “step”) on the surface, even if the interlayer insulating film deposited on the first wiring layer is flattened through a CMP process (a chemical mechanical polishing process for increasing the flatness of a surface). The step increases as the difference in the wiring area ratio of the first wiring layer increases. Moreover, the step which is caused by the difference in the wiring area ratio of the first wiring layer and remaining after the CMP process will not be significantly reduced even after a CMP process that is performed in preparation for the formation of lines in the third wiring layer. The steps occurring in the respective wiring layers accumulate to cause a so-called “global step” on the surface of the chip. Therefore, when the metal line
116
is provided as a multilayer line by using two or more wiring layers in order to further increase the acceptable current capacity, the global step between the I/O region and the central region of the chip increases. Typically, a plurality of chips are fabricated in a regular arrangement on a single wafer, and the I/O region of one chip adjoins the I/O region of another adjacent chip on the wafer.
FIG. 11
illustrates an arrangement of a plurality of chips on a wafer. In
FIG. 11
,
150
denotes a wafer, and a plurality of chips
151
are arranged on the wafer
150
. Each chip
151
includes an I/O region
152
surrounding a central region
153
of the chip. When fabricating such chips
151
each having the central region
153
surrounded by the I/O region
152
, as illustrated in
FIG. 11
, the I/O region
152
of one chip on the wafer
150
adjoins that of another adjacent chip. Therefore, when the wiring area ratio in the I/O region
152
is significantly larger than that in the central region
153
, a large area defined by two I/O regions
152
adjoining each other will have a large wiring area ratio on the waf
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