Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1998-09-24
2002-06-25
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C438S014000, C438S462000, C324S763010, C324S765010
Reexamination Certificate
active
06410936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that may be burned in on a wafer level in a semiconductor fabrication process, a fabrication method thereof, and a wafer burn-in method.
2. Description of the Prior Art
In general, a burn-in process is performed for semiconductor products in fabrication processes. During the burn-in process, the semiconductor products operate under a circumstance at a high temperature in order to eliminate defective semiconductor products in advance before shipping. It is thereby possible to increase the reliability of those semiconductor products. However, in the past, the burn-in process may be performed only after a molding process for each of a plurality of semiconductor chips obtained after a dicing process for a wafer on which the plurality of the semiconductor chips are formed. That is, there is a drawback in the past that it is difficult to perform the burn-in process in the wafer level or it is also difficult to perform the burn-in process for the state of semiconductor chips obtained after the dicing process. Furthermore, during the burn-in process, the semiconductor products obtained by the molding process must be connected to a plurality of sockets in a burn-in board. In addition, the semiconductor products are placed in a burn-in furnace and treated at a high temperature by supplying a high voltage in a continuous time period. Accordingly, it must be required to provide a plurality of sockets for the burn-in process of the semiconductor products. This causes to increase the cost of the burn-in board. Further, in general, because there is a limitation to the size of the burn-in furnace, the number of the semiconductor products to be treated simultaneously in the burn-in process is limited. Therefore the cost including the burn-in process becomes high and the time period required for the burn-in process is also long.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide semiconductor devices formed on a wafer, a fabrication method thereof, and a burn-in method. In the present invention, the semiconductor device may be burned in a wafer level efficiently, and semiconductor products assembled by an assembling process may also be burned in efficiently.
In accordance with a preferred embodiment of the present invention, a semiconductor device comprises a plurality of semiconductor chips formed on a wafer divided by dicing lines, and at least one power supply wiring to supply a power supply voltage formed on each of said dicing lines. Each of said semiconductor chips comprises a power supply voltage leading wiring connected to said power supply wiring, a burn-in mode (BI mode) detection circuit connected to said power supply voltage leading wiring for detecting the supply of the power supply voltage to said power supply wiring, and for generating a control signal and a BI mode detection signal indicating to enter said BI mode when the supply of the power source voltage to said power supply wiring, a self oscillation circuit for oscillating a clock signal having a predetermined frequency during the BI mode based on receiving of a BI mode signal, indicating to enter an operation of a burn-in process, transferred from said BI mode detection circuit, a timing generation circuit for receiving said clock signal and for generating a timing clock signal during said BI mode, a BI mode control circuit for receiving said timing clock signal and for transferring internal control signals to a plurality of internal circuits, incorporated in said semiconductor chip, to be executed under said BI mode, and a power supply circuit connected to said power supply voltage leading wiring for supplying said power supply voltage though said power supply wiring into said oscillation circuit, said timing generation circuit, said BI mode control circuit, and said plurality of internal circuits based on said control signal transferred from said BI mode detection circuit.
The semiconductor device as another preferred embodiment of the present invention, further comprises a first electrode region through which said power supply voltage is supplied and a second electrode region through which a ground voltage is supplied, both the first electrode region and the second electrode region are formed at a peripheral section of said wafer, wherein said second electrode region is electrically connected to a P− substrate layer through a P+ diffusion layer, and a P− diffusion layer of a N channel transistor in each of said semiconductor chips is electrically connected to said P− substrate layer, and the number of said power supply wiring formed on said dicing line is one and said power supply wiring on said dicing line is connected to said first electrode region.
In the semiconductor device as another preferred embodiment of the present invention, each of said plurality of semiconductor chips further comprises an input line, connected to said power supply wiring formed on said dicing line, independently from said power supply voltage leading wiring, to supply said power supply voltage into said BI mode detection circuit, and wherein said power supply voltage is directly supplied from said power supply wiring to said power source circuit through said power supply voltage leading wiring.
In the semiconductor device as another preferred embodiment of the present invention, said power source circuit comprises a transistor that enters ON when receiving said control signal transferred from said BI mode detection circuit during said BI mode and enters OFF in a mode other than said BI mode, wherein and said power source circuit supplies said power supply voltage to said self oscillation circuit, said timing generation circuit, said BI mode control circuit, and said plurality of internal circuit based on said the ON/OFF operation of said transistor.
In the semiconductor device as another preferred embodiment of the present invention, said transistor in said power source circuit is a P channel transistor, wherein said control signal transferred from said BI mode detection circuit is inputted to a gate of said P channel transistor.
In the semiconductor device as another preferred embodiment of the present invention, said transistor in said power source circuit is a N channel transistor, and said input line for supplying said power supply voltage from said power supply wiring to said BI mode detection circuit is directly connected to a gate of said N channel transistor.
In the semiconductor device as another preferred embodiment of the present invention, said BI mode detection circuit comprises a bonding pad for a wafer test formed on a node on said input line, and wherein a reversed voltage, whose voltage level is reversed to a voltage level of said power supply voltage supplied to said power supply wiring, is supplied to said bonding pad during execution of said wafer test.
In the semiconductor device as another preferred embodiment of the present invention, said BI mode detection circuit comprises a bonding pad for a wafer test formed on a node on said input line, and a pull down resistance or a pull up resistance is connected to said node on said input line, wherein a reversed voltage, whose voltage level is reversed to a voltage level of said power supply voltage supplied to said power supply wiring, is supplied to said bonding pad after dicing of said wafer.
In the semiconductor device as another preferred embodiment of the present invention, said BI mode detection circuit comprises at least two bonding pads, first bonding pad and a second bonding pad, connected to nodes on said input line, wherein a pull down resistance is connected to one of said bonding pads, and voltages of different levels are supplied to both said first bonding pad and said second bonding pad in order to melt said a wiring on said input line between said first bonding pad and said second bonding pad in said BI mode detection ci
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Tran Minh Loan
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