Semiconductor device

Details Semiconductor device Semiconductor device

2001-07-05

2002-11-26

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S226000, C365S189090

Reexamination Certificate

active

06487133

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-204104, filed Jul. 5, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device. More specifically, the invention relates to an overdrive power supply circuit used as a power supply circuit of a sense amplifier.
Conventionally, DRAM uses an overdrive power supply circuit (hereafter referred to as the overdrive circuit) for highly sensitive and fast sense operations. For a sense operation on a bit line, a sense amplifier's positive electrode is supplied with an electric potential (so-called overdrive potential) which is higher than a restoration potential for the bit line.
FIG. 12
shows a configuration example of a conventional overdrive circuit. In this figure, one external power supply (VCC)
101
connects with an overdrive potential generation circuit (VIIAG)
102
. The other external power supply (VCC)
103
connects with a restoration potential generation circuit (VAAG)
104
. The overdrive potential generation circuit
102
and the restoration potential generation circuit
104
connect with a switch circuit
105
. The switch circuit
105
connects with a sense amplifier driver (PSAD)
106
. The sense amplifier driver
106
connects with a sense amplifier (S/A)
107
. The sense amplifier
107
connects with a sense amplifier driver (NSAD)
108
. The sense amplifier driver
108
connects with an external power supply (GND)
109
.
The overdrive potential generation circuit
102
generates an overdrive potential (VIIA) for overdriving (amplifying) an electric potential of the bit line during a sense operation. This overdrive potential is also used as a power for peripheral circuits. The restoration potential generation circuit
104
generates a restoration potential (VAA) for restoring an electric potential of the bit line after the overdrive. The switch circuit
105
selects one of the overdrive potential and the restoration potential, and supplies it to the sense amplifier driver
106
.
FIG. 13
shows a configuration of the above overdrive circuit in more detail. The overdrive circuit needs to suppress output impedance. To configure the overdrive circuit using a MOS (Metal Oxide Semiconductor) transistor, a source follower (common drain amplifier) is used.
Normally, the overdrive potential generation circuit
102
and the restoration potential generation circuit
104
both generate a positive potential. Namely, the overdrive potential generation circuit
102
is configured by using an n-type MOS transistor
102
a
as a source follower. Namely, the restoration potential generation circuit
104
is configured by using an n-type MOS transistor
104
a
as a source follower.
The switch circuit
105
comprises p-type MOS transistors
105
a
and
105
b.
In this example, the p-type MOS transistors
105
a
and
105
b
also work as the sense amplifier driver
106
.
The sense amplifier
107
comprises p-type MOS transistors
107
a
and
107
b
and n-type MOS transistors
107
c
and
107
d
. The p-type MOS transistor
107
a
and the n-type MOS transistor
107
c
share the drain and are connected serially. The p-type MOS transistor
107
b
and the n-type MOS transistor
107
d
share the drain and are connected serially. A bit line BLt is connected to a connection point between the p-type MOS transistor
107
a
and the n-type MOS transistor
107
c
and gates of the p-type MOS transistor
107
b
and the n-type MOS transistor
107
d
. A bit line BLc is connected to a connection point between the p-type MOS transistor
107
b
and the n-type MOS transistor
107
d
and gates of the p-type MOS transistor
107
a
and the n-type MOS transistor
107
c
. The bit line BLc is complementary to the bit line BLt.
The power supply line
110
connects the sense amplifier
107
's positive electrode (connection point between sources of the p-type MOS transistors
107
a
and
107
b
) with the switch circuit
105
(connection point between drains of the p-type MOS transistors
105
a
and
105
b
). The sense amplifier driver
108
is connected to the sense amplifier
107
's negative electrode (connection point between sources of the n-type MOS transistors
107
c
and
107
d
). The sense amplifier driver
108
comprises an n-type MOS transistor
108
a.
FIG. 14
shows a layout structure of a DRAM memory core using the above overdrive circuit. Especially, the figure shows an arrangement of the overdrive circuit and its power supply wiring. AS shown in this figure, a plurality of cell arrays (cells)
111
is arranged in a matrix. The sense amplifiers
107
are placed on and under each cell array
111
along a row direction. The segment row decoders (SRD)
112
are placed to the right and left sides of each cell array
111
along a column direction. A circuit area (SSC
1
)
113
is provided at each intersection point between the sense amplifier
107
and the segment row decoder
112
.
A memory core periphery (one end of the column direction) is provided with a main row decoder (MRD)
114
corresponding to each column for the cell array
111
. A circuit area (SSC
2
)
115
is provided on and under each main row decoder
114
(row direction) corresponding to the circuit area
113
.
A memory core periphery (one end of the row direction) is provided with a plurality of overdrive potential generation circuit blocks
116
and a plurality of restoration potential generation circuit blocks
117
. In this example, each circuit block
116
comprises the overdrive potential generation circuit
102
(the n-type MOS transistor
102
a
) and the switch circuit
105
(the p-type MOS transistor
105
a
). Likewise, each circuit block
117
comprises the restoration potential generation circuit
104
(the n-type MOS transistor
104
a
) and the switch circuit
105
(the p-type MOS transistor
105
b
).
The circuit blocks
116
and
117
are connected to the sense amplifier
107
via the power supply line
110
. The power supply line
110
comprises, say, a first-level metal wire
110
a
and a second-level metal wire
110
b
. The metal wire
110
a
connects with the sense amplifier
107
's positive electrode. The metal wire
110
b
connects with the circuit blocks
116
and
117
. The metal wire
110
a
and the metal wire
110
b
are connected with each other in the circuit area
115
and the sense amplifier
107
.
However, the above configured overdrive circuit has the following problems.
1. An operation in a long RAS cycle requires a long restoration time. At this time, the potential level creeps, causing an excessively high restoration potential.
2. In the event of an excessive overdrive, there is a limited capability of decreasing an overdrive potential.
3. The overdrive potential generation circuit
102
is also used as the power supply circuit for the peripheral circuit. Because of this, a power supply noise during a sense operation propagates to the peripheral circuit.
4. There is a long distance between the restoration potential generation circuit
104
and the sense amplifier
107
. It takes time to supply a restoration potential.
As mentioned above, the prior art can provide highly sensitive and fast sense operations. When a bit line potential after the overdrive becomes too low or high with reference to the restoration potential, however, it is difficult to control this potential to a desired potential.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can stabilize a restoration potential level when the overdrive technique amplifies a bit line potential and the amplified bit line potential becomes too higher or lower than the restoration potential. It is also an object to provide a semiconductor apparatus which can easily control the overdriven bit line potential to a desired potential.
In order to attain the above objects, according to a first aspect of the present invention, there is p

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