Semiconductor device

Details Semiconductor device Semiconductor device

2000-04-06

2002-07-09

Wille, Douglas A. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C365S154000

Reexamination Certificate

active

06417545

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which includes a static random access memory having an access transistor and a driver transistor.
2. Description of the Background Art
Conventionally, the technique of opening a contact hole, which is formed in a self-alignment manner with a protection insulation film for covering a gate electrode, is used in a static random access memory (hereinafter, referred to as an SRAM). A conventional SRAM will be described in the following with reference to
FIGS. 7
to
9
.
An SRAM memory cell will be first described with reference to an equivalent circuit diagram shown in
FIG. 7. A
load transistor
103
a
and a driver transistor
102
a
are connected in series between a power supply electrode Vcc and a ground electrode GND. A load transistor
103
b
and a driver transistor
102
b
are also connected in series between power supply electrode Vcc and ground electrode GND. In other words, load transistor
103
a
and driver transistor
102
a
are connected in parallel with load transistor
103
b
and driver transistor
102
b
. The gate electrode of load transistor
103
a
is connected to the gate electrode of driver transistor
102
a
by an inter-gate interconnection. The gate electrode of load transistor
103
b
is also connected to the gate electrode of driver transistor
102
b
by an inter-gate interconnection.
The source/drain electrode of an access transistor
101
a
is connected to a portion for forming a storage electrode
106
a
between load transistor
103
a
and driver transistor
102
a
. The source/drain electrode of an access transistor
101
b
is connected to a portion for forming a storage electrode
106
b
between load transistor
103
b
and driver transistor
102
b.
Further, storage electrode
106
a
is connected to the inter-gate interconnection between load transistor
103
b
and driver transistor
102
b
, and storage electrode
106
b
is connected to the inter-gate interconnection between load transistor
103
a
and driver transistor
102
a
. The gate electrodes of access transistors
101
a
,
101
b
are connected to a word line
105
. The source/drain electrodes of access transistors
101
a
,
101
b
are connected to bit lines
104
a
,
104
b
, respectively.
A plan view of the SRAM structure will be described in the following. In
FIG. 8
, a region surrounded by a dash line corresponds to one memory cell. In the memory cell region, two access transistors
101
a
,
101
b
, two driver transistors
102
a
,
102
b
, and two load transistors
103
a
,
103
b
are formed.
On the main surface of the semiconductor substrate, the following impurity diffusion regions are formed. They are source/drain regions
112
d
,
112
a
of access transistors
101
a
,
101
b
, source/drain regions
112
f
,
112
c
of driver transistors
102
a
,
102
b
, source/drain regions
112
e
,
112
b
shared by access transistors
101
a
,
101
b
and driver transistors
102
a
,
102
b
, and source/drain regions
112
i
,
112
j
,
112
g
,
112
h
of load transistors
103
a
,
103
b.
Source/drain regions
112
a
,
112
b
,
112
c
,
112
d
,
112
e
,
112
f
are n-type active regions. Source/drain regions
112
g
,
112
h
,
112
i
,
112
j
are p-type active regions. On the semiconductor device, an isolation insulation film
111
is formed in a region other than source/drain regions
112
a
,
112
b
,
112
c
,
112
d
,
112
e
,
112
f
,
112
g
,
112
h
,
112
i
,
112
j
inside the dash line.
Gate electrodes which are each formed of the one-layer structure of a polycrystalline silicon film or the two-layer structure of a polycrystalline silicon film and a silicide film are formed as described below. A gate electrode
113
a
is formed between source/drain regions
112
a
,
112
d
and source/drain regions
112
b
,
112
e
. A gate electrode
113
b
is formed between source/drain regions
112
c
,
112
g
and source/drain regions
112
b
,
112
h
. A gate electrode
113
c
is formed between source/drain regions
112
f
,
112
j
and source/drain regions
112
e
,
112
i.
First contact plugs
114
a
,
114
b
are connected to source/drain regions
112
b
,
112
e
. First contact plugs
114
d
,
114
c
are connected to gate electrodes
113
b
,
113
c
. First contact plugs
114
g
,
114
e
,
114
f
,
114
h
are connected to source/drain regions
112
g
,
112
h
,
112
i
,
112
j
. A first metallic interconnection layer
115
a
is connected to the top surfaces of first contact plugs
114
a
,
114
c
,
114
e
. A first metallic interconnection layer
115
b
is connected to the top surfaces of first contact plugs
114
b
,
114
d
,
114
f
. A first metallic interconnection layer
115
c
is connected to the top surfaces of first contact plugs
114
g
,
114
h
. A first metallic interconnection layer
115
c
is connected to power supply electrode Vcc.
Second contact plugs
116
a
,
116
b
,
116
c
,
116
d
, which are formed in a self-alignment manner with a silicon nitride film (not shown) for covering gate electrodes
113
a
,
113
b
,
113
c
, are connected to source/drain regions
112
a
,
112
c
,
112
d
,
112
f
. Second metallic interconnection layers
117
a
,
117
b
,
117
c
,
117
d
are formed on the top surfaces of second contact plugs
116
a
,
116
b
,
116
c
,
116
d.
A sectional structure of the conventional SRAM having the above described plan structure will be described in the following. As can be seen from
FIG. 9
for illustrating the sectional structure taken along line IX—IX in
FIG. 8
, a semiconductor substrate
121
has a p-type well
122
which is formed from the main surface to a prescribed depth. An isolation insulation film
111
for isolating and forming element formation regions is formed from the position of a prescribed height from the main surface of semiconductor substrate
121
to the position of a prescribed depth in semiconductor substrate
121
.
In the element formation regions, gate electrodes
113
b
,
113
c
are formed on the main surface of semiconductor substrate
121
with a gate insulation film therebetween. Sidewall nitride films
124
a
,
124
b
,
124
c
,
124
d
are formed on the sidewalls of gate electrodes
113
b
,
113
c
. In the element formation regions, n
−
impurity regions
112
q
,
112
r
,
112
s
,
112
t
of a relatively low impurity concentration and n
+
impurity regions
112
n
,
112
k
,
112
m
,
112
p
of a relatively high impurity concentration are formed from the main surface of semiconductor substrate
121
to a prescribed depth. Here, n
−
impurity region
112
q
and n
+
impurity region
112
m
form source/drain region
112
c
, n
−
impurity region
112
r
and n
+
impurity region
112
k
form source/drain region
112
b
, n
−
impurity region
112
s
and n
+
impurity region
112
n
form source/drain region
112
e
, and n
−
impurity region
112
t
and n
+
impurity region
112
p
form source/drain region
112
f.
A silicon nitride film
126
is formed to cover gate electrodes
113
b
,
113
c
, sidewall nitride films
124
a
,
124
b
,
124
c
,
124
d
, isolation insulation film
111
, and the main surface of semiconductor substrate
122
. An interlayer insulation film
125
a
is formed on silicon nitride film
126
.
In contact holes which pass through interlayer insulation film
125
a
and silicon nitride film
126
and reach n
+
impurity regions
112
n
,
112
k
, first contact plugs
114
a
,
114
b
are formed. First metallic interconnection layers
115
a
,
115
b
are formed to connect to the top surfaces of first contact plugs
114
a
,
114
b
. An interlayer insulation film
125
b
is formed to cover first metallic interconnection layers
115
a
,
115
b
and interlayer insulation film
125
a
. In contact holes which pass through interlayer insulation films
125
a
,
125
b
and silicon nitride film
126
and reach n
+
impurity regions
112
m
,
112
p
, second contact plugs
116
c
,
116
d
are formed. Second metallic interconnection layers
117
c
,
117
d
are formed to connect to the

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