Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-18
2002-06-11
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000, C257S401000, C257S403000, C257S488000
Reexamination Certificate
active
06404015
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device with a MOS transistor of the depletion type comprising a semiconductor body with a semiconductor layer of a first conductivity type adjoining a surface of said body, a semiconductor substrate situated at the side of the semiconductor layer facing away from the surface, and a layer of electrically insulating material, referred to as insulating layer hereinafter, disposed between the semiconductor layer and the semiconductor substrate, which semiconductor layer is provided with a source and a drain in the form of surface zones of the first conductivity type which are mutually separated by an interposed channel region of the first conductivity type, while the surface is covered with a gate dielectric on which a gate electrode is provided. Such a device is known, inter alia, from the patent document U.S. Pat. No. 4,611,220.
Transistors of the kind described above, in which the conduction between the source and the drain is controlled by means of a depletion region in the channel induced by the insulated gate, are often denoted deep depletion MOS transistor in the literature. If the transistor is of the n-channel type, a voltage of 0 V or lower with respect to the source is usually applied to the gate. Given a sufficiently high drain voltage, the depletion region at the drain side of the channel will expand to the extent that the channel is pinched, so that the current between source and drain rises no further upon a further increase in the drain voltage. This (current-independent) voltage will be referred to as the pinch voltage below.
Such transistors may advantageously be used as voltage reducers in the supplies of, for example, integrated circuits. High-voltage circuits (or high current circuits) are often used in a common silicon crystal in so-called Smart Power IC processes, in combination with control circuits which are operated at low voltages or considerably lower voltages than the high-voltage components. These low-voltage circuits often require a much lower supply voltage than the externally supplied voltage for the integrated circuit, for example the rectified mains voltage. The pinch voltage of the deep depletion MOS transistor connected as a source follower can be used for obtaining this lower supply voltage.
The patent document U.S. Pat. No. 4,611,220 cited above describes a deep depletion MOS transistor in SOI (Silicon On Insulator) technology. The carrier body used in the known device is a silicon substrate which is covered with a sapphire layer. The semiconductor layer in which the transistor is formed is an n-type silicon layer which is provided epitaxially on the sapphire layer and is provided with strongly doped n-type surface zones which form the source and the drain. The gate dielectric is formed by a silicon oxide layer on which the gate electrode is provided. To prevent inversion occurring at the boundary between the channel region and the gate oxide during operation as a result of the generation of minority charge carriers,—holes in the case of an n-channel transistor—, p-type surface zones are locally provided in the channel region, which zones extend from the surface over part of the thickness of the epitaxial layer into the epitaxial layer. As is described in the patent document, an inversion layer would be formed below the gate without these p-type zones, hampering a satisfactory operation of the transistor because the thickness of the depletion layer cannot or substantially cannot be controlled any more by means of the gate voltage after the inversion layer has been formed. The inversion layer below the gate can be prevented through the removal of the holes via said p-type zones.
The research on which the present invention is based has shown that the transistor cannot or substantially cannot be brought into a stable pinch state at higher voltages, for example a few hundreds of volts, also with the use of a removal mechanism for minority charge carriers as described above.
SUMMARY OF THE INVENTION
The invention has for its object inter alia to provide a deep depletion SOI MOS transistor which can be operated also at higher voltages such that pinching takes place, and which can accordingly be used, for example, for generating a lower supply voltage in integrated high-voltage circuits with a high external supply voltage.
According to the invention, a semiconductor device of the kind described in the opening paragraph is for this purpose characterized in that the semiconductor layer is provided with at least one zone of the opposed, second conductivity type for the purpose of removing minority charge carriers from the channel region, which zone is provided with an electrical connection, forms a pn junction with the channel region, and extends transversely across the thickness of the semiconductor layer between the surface and the insulating layer.
The invention is based on the recognition inter alia that at higher voltages the (conductive) semiconductor substrate, which is separated from the channel by a comparatively thick insulating layer, also acts as a gate, so that also at the other side of the semiconductor layer opposite the surface an inversion layer can be formed which counteracts a total pinching of the channel. Since said zones of the second conductivity type in a device according to the invention extend across the entire thickness of the semiconductor layer, minority charge carriers can also be removed at the boundary between the semiconductor layer and the insulating layer at the substrate side, so that the channel can be pinched also at higher voltages.
A major embodiment of a device according to the invention is characterized in that the semiconductor layer is provided, next to said zone of the second conductivity type which is referred to as first zone hereinafter, with a second zone of the second conductivity type which is situated next to the first zone, which also extends across the entire thickness of the semiconductor layer, which forms a pn junction with the channel region, and which is separated from the first zone of the second conductivity type by an interposed portion of the channel region, the interspacing between said zones in relation to the thickness of the semiconductor layer being so great at the area of the channel region that pinching of the channel in lateral direction is prevented. The width of the channel can be optimally designed in that the channel is provided with two or more zones for the removal of minority charge carriers, for example with a view to the desired current-conducting power in a certain application of the transistor. The provision of the zones at a sufficiently great distance from one another can prevent then that the channel is pinched in lateral direction through depletion of the channel from the pn junctions between the channel and the zones of the opposed conductivity type, which would make the pinch voltage undesirably low. A further embodiment thereof, which has the advantage of an efficient removal of minority charge carriers over the entire channel width between the zones, is characterized in that the interspacing between the two zones is so small that the application of a reverse bias voltage across the pn junctions between the zones of the second conductivity type and the channel region of the first conductivity type is capable of inducing an electric field with a component directed to one of the zones of the second conductivity type, which field extends over the full interspacing between said zones.
A further embodiment of a semiconductor device according to the invention is characterized in that a drift region is situated in the semiconductor layer between the channel region and the drain. The drift region raises the breakdown voltage of the transistor, which renders the circuit suitable for operation at very high voltage values. The electric field in the drift region will drive majority charge carriers to the drain, and minority charge carriers generated in the drift region will be driven to the channel region, w
Emmerik Arnoldus Johannes Maria
Van Zwol Johannes
Zingg Rene Paul
Koninklijke Philips Electronics , N.V.
Ngo Ngan V.
Waxler Aaron
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