Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-02-09
2002-04-09
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S673000, C257S777000, C257S786000, C257S775000
Reexamination Certificate
active
06369407
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor substrate and having connection pads formed thereon for achieving connection with a semiconductor chip or the like.
2. Description of the Prior Art
In semiconductor devices, to achieve further miniaturization and higher integration density, three-dimensional structures have been proposed to supersede conventional two-dimensional structures. However, forming semiconductor devices having a three-dimensional structure by a continuous process usually results in an unacceptably low yield and involves various difficulties.
To overcome such problems, the inventors of the present invention have been working on a way to commercialize semiconductor devices having a so-called chip-on-chip structure, i.e. a semiconductor device in which a plurality of semiconductor chips are bonded together in a two-layer structure with the surface of a first semiconductor chip laid on the surface of a second semiconductor chip.
To bond a pair of semiconductor chips together, for example, bumps made of an oxidation-resistant metal such as gold are formed on one semiconductor chip. These bumps serve to achieve electrical connection between the electric circuits formed on the two semiconductor chips and simultaneously achieve mechanical bonding between the two semiconductor chips.
FIG. 4
is an enlarged perspective view of the structure of a portion around bumps formed on a semiconductor chip. On the surface
101
of a semiconductor chip
100
, i.e. on that side thereof on which an active surface-layer region lies in which transistor and other devices are formed, pads
102
are formed that are connected to the internal circuit (not shown) formed inside the semiconductor chip
100
. On these pads
102
, bumps
103
made of gold or the like are formed so as to protrude upward. Before the semiconductor chip
100
is assembled with another semiconductor chip by being bonded together, it is singly subjected to a functional test to check its functions. This test is conducted with the tip of a test probe
110
pressed on the bumps
103
.
Here, pressing the test probe
110
damages the bumps
103
as indicated by reference symbol A, deforming the surface of the bumps
103
or forming a scooped-out or curled-up portion in the material of the bumps
103
. In particular, for example, in cases where the functional test needs to be repeated two or three times under different temperature conditions, the test probe
110
needs to be pressed onto the bumps
103
a plurality of times, and accordingly, when the semiconductor chip
100
has gone through the functional test, the bumps
103
may have suffered considerable damage.
A bump
103
thus damaged cannot secure proper bonding between two semiconductor chips, with the result that the semiconductor chips, when bonded together, suffer from bad contact, making the resulting semiconductor device having a chip-on-chip structure defective as a whole.
Damage to the bumps
103
can be avoided by conducting the functional test before forming the bumps
103
. However, in that case, the test probe
110
needs to be pressed onto the pads
102
, and thus damage to the pads
102
is inevitable. It is difficult to form a bump
103
properly on a pad
102
thus damaged, with the result that semiconductor chips cannot be bonded together properly. It is possible to form a bump
103
properly even on a damaged pad
102
if the bump
103
is formed as a considerably thick film. However, this requires an extra amount of material and time to form the bump
103
, and thus cannot be said to be a desirable solution.
Japanese Laid-Open Patent Application No. H7-122604 proposes providing test pads for the functional testing of a semiconductor chip separately from connection pads. This makes it possible to conduct the functional testing of a semiconductor chip by the use of ordinary testing equipment, and in addition to achieve reliable bonding of metal wires, which contributes to accommodating a larger number of pins.
This prior-art technique helps avoid damage to connection pads, and is thus effective in achieving proper bonding between semiconductor chips. However, within the internal device region, the connection pads occupy an unduly large area, and thus degrade the integration density of the internal devices.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that permits semiconductor chips that have gone through a functional test to be bonded together properly without sacrificing the integration density of the internal devices.
To achieve the above object, according to the present invention, a semiconductor device is provided with a semiconductor substrate; an internal circuit formed on the semiconductor substrate; a connection pad formed on the semiconductor substrate and connected to the internal circuit; and a test pad formed on the semiconductor substrate so as to be connected to the connection pad and used for functional testing of the internal circuit. Here, the semiconductor substrate has a bonding region provided on the surface thereof so as to allow another semiconductor substrate to be superposed thereon by being bonded thereto, with the connection pad formed inside the bonding region and the test pad formed outside the bonding region.
In this structure, the connection pad that is connected to the internal circuit is also connected to the test pad. Therefore, it is possible to conduct the functional testing of the semiconductor device by using the test pad and thus without causing any damage to the connection pad. Accordingly, it is possible to achieve proper bonding between the semiconductor device having undergone the functional testing and another semiconductor chip or the like.
Moreover, the test pad can be formed in a position best suited for the functional testing, and the connection pad can be formed in a position best suited for connection with another semiconductor chip or the like. This allows free setting of the positions in which connection with another semiconductor chip or the like is achieved.
In this semiconductor device according to the present invention, the connection pad may be so formed as to have a smaller size than the test pad.
This structure helps minimize the area occupied by the connection pad within the internal device region, and thus helps achieve proper connection between the semiconductor device having undergone the functional testing and another semiconductor chip or the like without sacrificing the integration density of the internal devices.
REFERENCES:
patent: 4951098 (1990-08-01), Albergo
patent: 5726500 (1998-03-01), Duboz
patent: 5891745 (1999-04-01), Dunaway
patent: 6008061 (1999-12-01), Kasai
patent: 7-122604 (1995-05-01), None
Hikita Junichi
Mochida Hiroo
Shibata Kazutaka
Jackson, Jr. Jerome
Rohm & Co., Ltd.
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