Semiconductor device

Details Semiconductor device Semiconductor device

2000-03-24

2002-05-21

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S048000, C257S773000, C257S775000

Reexamination Certificate

active

06392307

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device, and relates in particular to a semiconductor device, which is appropriate for driving an electret condenser microphone.
2. Description of the Prior Art
An electret condenser microphone (ECM) is element, which is used to convert aerial vibrations such as voice to electric signals representing changes in capacitance values. Because its output signal is very weak, an element for amplifying the output signal of the ECM is required to have characteristics of high input impedance, high gain, and low noise.
There are elements that satisfy these requirements, which are the junction field-effect transistor (J-FET) and the metal-oxide semiconductor field-effect transistor (MOSFET). As described in Japanese Laid-Open Patent Publication 58-197885, for example, especially the J-FET element is easily mountable to be integrated in a bipolar integrated circuit.
FIG. 1
shows a cross-section of a p-channel J-FET device. As shown in the diagram, the J-FET device includes a p-type substrate
1
; an n-type epitaxial layer
2
deposited on the substrate
1
; an n
+
-type buried layer
3
formed between the substrate
1
and epitaxial layer
2
; a p
+
-type isolation region
4
penetrating from the surface of the epitaxial layer
2
into the substrate
1
and surrounds the buried layer
3
to form an island region
5
.
An n
+
-type top gate region
6
is formed in the surface of the island region
5
. A p-type channel region
7
is formed below the top gate region
6
. A p
+
-type source region
8
is formed on one end of the channel region
7
, and a p
+
-type drain region
9
is formed on the other end. Highly concentrated n
+
-type gate contact regions
10
are formed on the outside of the source region
8
and drain region
9
, respectively.
An insulating film
16
is deposited on the top surface of the entire device. A source electrode
11
S, drain electrode
11
D, and gate electrode
11
G are connected to above mentioned regions
8
,
9
,
10
respectively through the insulating film
16
. The resulting configuration is that of a conventional p-channel J-FET.
According to the p-channel J-FET, a pn junction is formed in the gate region. Hence, the junction can be reverse-biased to control the width of the depletion layer and restrict the drain current.
When integrating other functions in the semiconductor device, a p-type base region
12
, an n
+
-type emitter region
13
, and an n
+
-type collector contact region
14
are formed in another island region
5
, which works as an npn bipolar transistor. The npn transistor processes signals received by the J-FET element, acting as an element of overall construction of an integrated network.
However, when the elements above mentioned are used to amplify signals from an ECM, it may be required to provide an extended electrode
15
in the device that has a surface area much larger than that of the device's electrode pads.
This construction generates a parasitic capacitance C
1
between the extended electrode
15
and epitaxial layer
2
sandwiching the insulating film
16
therebetween, and a pn junction capacitance C
2
between the epitaxial layer
2
and substrate
1
. These capacitances are connected to a substrate-biased ground potential GND. The values of these capacitances can reach as much as several tens of pF, which is a level that cannot be ignored.
FIG. 2
shows a schematic circuit diagram including capacitances C
1
and C
2
. The ECM is connected on one end to a gate (input terminal) of a J-FET
17
. The source electrode of the J-FET
17
is grounded. The drain electrode of the J-FET
17
is connected to an output terminal OUT. The output terminal OUT is connected to an integrated network, including an npn transistor or the like that is formed on the same substrate. The capacitances C
1
and C
2
described above are connected in series between the gate electrode of the J-FET
17
and the ground potential. Accordingly, signals output from the ECM flow to the ground via the capacitances C
1
and C
2
, as illustrated in the diagram by a current i. As a result, the signal level applied to the gate electrode of the J-FET
17
drops, thus the desired output voltage can not be obtained.
Sometimes it is required to add a test pad for measuring the properties of the input transistor during the fabrication process. As shown in
FIG. 3
, a test pad
18
is formed on the insulating film
16
, as with the extended electrode
15
shown in
FIG. 1
, and connects to the gate electrode
11
G of the input J-FET for testing the behavior of the J-FET before shipping. As with the input/output pads of the integrated network, the test pad
18
is usually formed in a rectangular shape with one side measuring 100-300 &mgr;m. The p
+
-type isolation region
4
is formed on the underside of the test pad
18
. As a result, a parasitic capacitance C
3
is generated by the test pad
18
and the isolation region
4
. This capacitance C
3
is connected in parallel to the capacitances C
1
and C
2
, as shown in
FIG. 2
, further increasing leakage in the current flowing to the ground potential GND.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a semiconductor device, which is able to provide a desired output voltage of the ECM without signal loss caused by parasitic capacitances.
To achieve the object of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; integrated network elements including an input transistor being integrated on the semiconductor substrate, the input transistor having an input terminal; a first bonding pad connected to the input terminal of the input transistor for testing properties of the input transistor; a second bonding pad connected to one of the integrated network elements for external connection; and a surface area of the first bonding pad being smaller than that of the second bonding pad.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of example.


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