Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-20
2003-09-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06625792
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Japanese Patent Application No. 11-221338, which was filed in the Japanese Patent Office on Aug. 4, 1999, and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a large-scale integration (“LSI”) design system, and to an LSI design system utilizing Computer Aided Design (“CAD”). More particularly, the present invention relates to a system, circuit and method for enhancing macro and module layout with respect to power supply wiring on an LSI semiconductor chip using CAD.
In the design process of a semiconductor chip, and after the specifications of the semiconductor chip are determined, division to a plurality of modules is performed on the basis of the determined specifications. Modules, i.e. module units, are then blocked to realize predetermined functions. Modules include macros such as RAM, ROM, CPU, etc., and unit cells such as AND gates, OR gates, flip-flops (“FF”), etc. The semiconductor chip is therefore comprised of these modules.
As illustrated,
FIG. 32
provides an illustration of a problem to be solved by the present invention and an effect of the present invention. Flow of a design process of a semiconductor chip is first explained. A module group is generated from specifications
100
of a semiconductor chip. The specifications
100
are described in a Register Transfer Level (“RTL”) description in an operation level logical circuit
101
. Thereafter, function and logical design is performed.
The RTL description in operation level logical circuit
101
is converted to a net list (gate level logical circuit)
103
by logical synthetic
102
. Next, a physical design is performed on a module group, which has been converted to the net list. The module group is physically arranged on the semiconductor chip based on the net list
103
by way of layout unit
104
. The layout unit
104
also performs layout wiring.
A problem occurs when a module including macros is arranged at an area near the center of a semiconductor chip. That is, because a macro is very large compared to an individual unit cell, and because wiring cannot pass through the macro, wiring must be made through an alternative route to avoid conflicts. Wiring efficiency is then lowered.
Therefore, when layout of a module is completed, the layout distribution of modules must be checked. This layout distribution check is performed in some cases by a method such as simulation, but is often performed visually for the result of actual layout of the net list. If some problems occur in the layout distribution of modules, a design process must be repeated from the stage of function and logical design in view of modifying layout distribution of modules. In some cases, the RTL description itself must be described again.
As explained above, in the related art, a discrepancy in layout of modules and macros is detected for the first time in the process of a physical design stage. Therefore the design process must be returned to the function and logical design stage for re-arrangement. This process results in a long term process for semiconductor design because of the need for repeated design processes. In the future, design process time will increase in response to an expected increase in the number of modules and an enlargement in circuit scale. Moreover, a new problem will be presented in that reliability will be lowered because of an increased possibility of miscalculation of available chip area. Further, predictability of a chip design price will be compromised due to miscalculation of available chip area.
BRIEF SUMMARY OF THE INVENTION
According to the present semiconductor design system, accurate module layout position information is obtained in a stage where the specifications are determined, i.e. before entering the function and logical design stage for the chip. Repetition of design can also be avoided by suppressing generation of problems in the subsequent function, logical design and physical design stages.
FIG. 32
illustrates an effect of the present invention. Before starting a detailed chip design, namely in the stage where the specifications
100
are determined (i.e., in the stage before generation of the RTL description), accurate layout position information of modules can be obtained. Therefore, because chip area and chip price can be estimated quickly and accurately, quick correspondence can be made to customers. Moreover, because subsequent design may be performed based on the accurate layout position of modules, repetition of a design process can be avoided due to suppression of design problems.
When module size, i.e. a number of areas, is included in the specifications, the layout position information of a module considering module size, can be obtained. Therefore, more accurate estimation of chip area and chip price can be obtained. Likewise, when module size is included in the specifications, the terminal position information of a module can also be obtained. Therefore, a highly accurate layout wiring process can be performed. A module, including macros, can be arranged along a side of a semiconductor chip and wiring efficiency and chip integration density can also be improved.
A semiconductor design system enhances layout on a semiconductor chip with a determining unit determining a layout position of a module on a semiconductor chip based on design information comprising information for connecting an external circuit to the module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip. A module moving unit moves the module having the associated macro to an area near a side of the semiconductor chip. The design information further includes information about a size of the module, and the module layout position is determined by considering the size of the module.
In a semiconductor design system according to the present invention, an input/output pad of a semiconductor chip is divided into a plurality of pad allocation areas, and a determining unit generates information of a terminal position for connecting modules on the semiconductor chip. Macros included in a module are allocated with a longest side length macro disposed toward a side of the semiconductor chip and remaining macros sequentially disposed toward chip center in order of macro length. Further, the chip is divided into four areas, with each area having an associated corner of the chip, and wherein the module having the longest sided macro among the modules in each area is allocated at a corresponding corner of the chip. The same type of macros within a module are disposed with signal terminals opposed to each other when arranged adjacently.
A semiconductor design system has a module initial layout unit allocating a module to an initial predetermined position on a semiconductor chip, a first module moving unit moving the module to an area closer to a pad allocating area of a plurality of pad allocation areas based on information for connecting an external circuit and the module, a second module moving unit moving the module based on information of connecting the module with a plurality of other modules, a third module moving unit moving modules having macros to areas near a side of the chip, a macro layout unit allocating macros to corresponding areas within each module, and a macro moving unit moving macros within each module to remove macro overlap.
REFERENCES:
patent: 5537332 (1996-07-01), Bolliger et al.
patent: 5731985 (1998-03-01), Gupta et al.
patent: 5793644 (1998-08-01), Koford et al.
patent: 5808901 (1998-09-01), Cheng et al.
patent: 5930147 (1999-07-01), Takei
patent: 6286128 (2001-09-01), Pileggi et al.
Su et al, “A Timing-Driven Soft-Macro Placement and Resynthesis Metehod in Interaction with Chip Floorplanning,” IEEE, Apr. 1999, pp. 475-483.
Fujitsu Limited
Siek Vuthe
Staas & Halsey , LLP
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