Semiconductor design support apparatus

Details Semiconductor design support apparatus Semiconductor design support apparatus

2006-12-08

2010-11-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07840922

ABSTRACT:
The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of symmetry orthogonal to the first axis. The recognition pattern is asymmetric to both first and second axes. The layout execution unit determines the layout of a macrocell including the recognition pattern to generate layout pattern data. The layout verification unit read the pattern data of the recognition pattern included in the macrocell based on the layout pattern data and verify the arrangement direction of the macrocell based on the recognition pattern.

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