Semiconductor data storage apparatus

Details Semiconductor data storage apparatus Semiconductor data storage apparatus

2001-06-19

2003-09-30

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S903000, C257S206000

Reexamination Certificate

active

06627960

ABSTRACT:

FIELD OF THE INVENTION
The present invention in general relates to a semiconductor storage apparatus comprising a SRAM (Static Random Access Memory) memory cell. In particular, this invention relates to the semiconductor storage apparatus for improving soft error resilience.
BACKGROUND OF THE INVENTION
In recent years, there is an increasing demand for lighter and thinner electronic devices which function at high-speed. At present, a microcomputer must be mounted in such electronic devices. The constitution of the microcomputer requires a large-capacity and high-speed memory. In view of the rapid proliferation of high-performance personal computers, there is a demand for a large-scale cache memory in order to achieve high-speed processing. That is, there is a demand for a high-speed and large-scale RAM which is used by a CPU when executing control programs and the like.
Generally, a DRAM (Dynamic RAM) and an SRAM (static RAM) are used as the RAM. The SRAM is usually used as the section needed for high-speed processing such as the cache memory mentioned above. Two types of SRAM memory cell constitutions are known. The two types are, a high-resistance load type comprising four transistors and two high-resistance elements, and a CMOS comprising six transistors. These days the CMOS SRAM is used more often since it has extremely low current leakage when holding data and is consequently highly reliable.
FIG. 55
is a circuit diagram showing a memory cell of a conventional CMOS SRAM.
FIG. 55
shows only the circuit sections of the memory cell which maintain memory, and omits the MOS transistor for access which is needed for reading and writing the memory status. As shown in
FIG. 55
, the memory cell can be expressed by two inverters INV
1
and INV
2
which connect an input terminal and an output terminal in complement.
FIG. 56
is a circuit diagram showing the internal circuit constitution of the inverters INV
1
and INV
2
, that is, a MOS inverter circuit. As shown in
FIG. 56
, each of the inverters INV
1
and INV
2
comprises one PMOS transistor PM
1
and one NMOS transistor NM
1
. The source of the PMOS transistor PM
1
is connected to a power line V
DD
and the source of the NMOS transistor NM
1
is connected to a ground line GND. The drains of the two transistors are connected together. These commonly connected drains form an output terminal OUT. The gates of the two transistors are connected together. These commonly connected gates form an input terminal IN. The inverter function is realized by a CMOS constitution wherein the PMOS transistor PM
1
functions as a load transistor and the NMOS transistor NM
1
functions as a drive transistor.
The operation of the CMOS inverter circuit shown in
FIG. 56
will be explained. When a potential at high logical level (hereafter, “H”), i.e. V
DD
potential, is applied to the input terminal IN, the PMOS transistor PM
1
switches OFF and the NMOS transistor NM
1
switches ON.
Consequently, the output terminal OUT is electrically connected via the NMOS transistor NM
1
to the ground line, and its potential becomes low logical level (hereafter, “L”), i.e. GND potential. Conversely, when a potential at logical level “L”, i.e. the GND potential, is applied to the input terminal IN, the NMOS transistor NM
1
switches OFF and the PMOS transistor PM
1
switches ON. Consequently, the output terminal OUT is electrically connected via the PMOS transistor PM
1
to the power line, and its potential becomes logical level “H”, i.e. the V
DD
potential. Thus, there is a complementary relationship between the logic of the input and output of the CMOS inverter circuit.
Subsequently, the conventional memory cell shown in
FIG. 55
will be explained. The input terminal of the inverter INV
1
and the output terminal of the inverter INV
2
are connected together, and the output terminal of the inverter INV
1
and the input terminal of the inverter INV
2
are connected together. Therefore, there is a complementary relationship between the memory nodes NA and NB in FIG.
55
.
For instance, when the storage node NA has a potential of logical level “H”, the storage node NB is stable at a potential of logical level “L”, and vice versa. In this way, the memory cell comprising the inverters has two different stable logical states depending on whether the two storage nodes NA and NB are at the “H” or “L” levels, and the logical state of the memory cell is held as one bit of stored data.
The semiconductor storage apparatus comprising the CMOS inverter circuit has extremely good stability and so far there have been no problems regarding noise tolerance. However, in the case of a large-capacity memory formed by integrating a great number of memory cells such as that described above, the memory cell area per bit becomes extremely small, affecting the charge generated when the circuit is struck by ionizing radiation. That is, the storing status of the memory cells is made unstable by the emission of radiation, increasing the possibility of errors such as inverted data storage.
This phenomenon is termed a “soft error” and is caused by &agr; rays which are emitted from the materials used for packaging and inter connections. A soft error is particularly likely to occur as the power voltage decreases. For this reason, the matter of how to increase tolerance against soft errors is an important issue in recent semiconductor storage apparatuses which are driven at low power.
Various semiconductor storage apparatuses wherein soft-error tolerance is increased by increasing the capacitance of the storage nodes have been proposed. For example, according to the “semiconductor memory apparatus” disclosed in Japanese Patent Application Laid-Open No. 9-27046, a capacitor is formed by inserting a thin active region between the storage nodes (i.e. the connections between the gates of the driving transistors and the gates of the load transistors forming the CMOS inverter) and the semiconductor substrate, thereby increasing the capacitance of the storage node sections.
On the other hand, there is a nonvolatile semiconductor storage apparatus comprising a memory cell for SRAM, a transistor for access and several capacitors. In this nonvolatile semiconductor storage apparatus, the capacitance of the storage nodes is an important matter.
According to this nonvolatile semiconductor storage apparatus, the potential is determined by dividing the capacitance of the multiple capacitors and data is written. The relative sizes of the capacitances of the capacitors connected at the nodes is read when the power is switched ON. Therefore, it has been difficult to suitably design the capacitors. Japanese Patent Application Laid-Open No. 62-33392 discloses a “nonvolatile semiconductor storage apparatus” in which the capacitors are eliminated by connecting the gate of an MOS transistor having a floating gate to the storage node of the SRAM memory cell instead of the capacitor, thereby forming a nonvolatile memory section.
However, in order to meet demands for a more highly-integrated semiconductor storage apparatus having larger capacity, the constituent elements of the memory cell must be made minute. This leads to the disadvantages that the capacitance of the storage node section becomes even smaller, increasing the possibility of soft errors.
To solve this problem, conventional memory cells such as that disclosed in Japanese Patent Application Laid-Open No. 9-270469 described above must use a specific semiconductor layout pattern in order to increase the capacitance of the storage node sections. The process of redesigning the layout pattern so as to cope with high integration of the memory cell in the future are complex, and there may not be any easy solutions.
According to the “nonvolatile semiconductor storage apparatus” disclosed in Japanese Patent Application Laid-Open No. 62-33392 mentioned above, the MOS transistor connected to the storage node of the SRAM memory cell comprises a nonvolatile memory section, and consequently must have a layout enabling a floating gate to be provided. Moreover, th

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