Semiconductor crystalline laminate structure, forming method of

Details Semiconductor crystalline laminate structure, forming method of Semiconductor crystalline laminate structure, forming method of

1994-08-08

1996-02-27

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

With lattice constant mismatch

257 18, 257 20, 257194, 257 22, 257191, 372 45, H01L 29205, H01L 29778

Patent

active

054951151

ABSTRACT:
A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the method are indicated.

REFERENCES:
patent: 4984242 (1991-01-01), Scifres et al.
IBM TDB vol. 36 No. 3 Mar. 1993 pp. 127-129 "Si/SiGe Heterostructure . . . SiGe Channel".
Sagawa et al Elec. Letts 13 Aug. 92 vol. 28 No. 17 pp. 1639-1640 "Confinement Layer . . . High Temp.".

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