Semiconductor contact via structure and method

Details Semiconductor contact via structure and method Semiconductor contact via structure and method

1992-02-06

1993-09-21

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437947, 156653, H01L 21302

Patent

active

052468836

ABSTRACT:
A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

REFERENCES:
patent: 4372034 (1983-02-01), Bohr
patent: 4824767 (1989-04-01), Chambers et al.
patent: 5041397 (1991-08-01), Kim et al.

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