Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-08-29
2003-04-29
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S211000, C365S052000
Reexamination Certificate
active
06556496
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor configuration having a control unit, which subjects a semiconductor module of the semiconductor configuration to a refresh cycle with a refresh time which is set in such a way that, at the highest semiconductor module temperature to be expected, the retention time of the semiconductor module is longer than the refresh time. Such a semiconductor module is preferably a dynamic random access memory (DRAM).
In the case of a DRAM as an example of a volatile semiconductor memory, the internal time constant thereof, the so-called retention time, specifies the time duration within which the individual memory cells of the DRAM must he subjected to a refresh in order to avoid a loss of data. In this case, the refresh time must be shorter than the retention time.
In the case of a DRAM, then, the retention time of its memory cell is greatly influenced by the temperature. In other words, the retention time is shorter, the higher the temperature of the DRAM.
As is known, however, DRAMs are used in a very broad temperature range. In order to avoid a loss of data in all cases, the refresh cycle in the case of DRAMs is therefore set in such a way that, at the highest temperature to be expected, that is to say 70° C. for example, the retention time is longer than the refresh time. A suitable value for the refresh time for this purpose is 64 ms, for example. Such a refresh time ensures that even at high temperatures of the order of magnitude of 70° C., the retention time is longer than the refresh time, as a result of which the loss of data can be avoided.
If a DRAM is operated at temperatures, which are lower than the maximum temperature to be expected of 70° C., for example, then the memory cells of the DRAM are subjected to a refresh more often than would actually be necessary. In other words, the current consumption of the DRAM is increased and the system performance of the DRAM is reduced.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor configuration with an optimized refresh cycle that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the refresh cycle is adapted to the actual requirement necessary for the data refresh.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor configuration containing a semiconductor module having housing pins and a control unit connected to the semiconductor module and subjecting the semiconductor module to a refresh cycle with a refresh time set such that, at a highest semiconductor module temperature to be expected, a retention time of the semiconductor module is longer than the refresh time. A temperature sensor is disposed in the semiconductor module and is connected to one of the housing pins. The temperature sensor measures a temperature of the semiconductor module and reports the temperature to the control unit. The control unit adapting the refresh time of the refresh cycle to the retention time expected for the semiconductor module at the temperature measured.
In the case of a semiconductor configuration of the type mentioned in the introduction, the object is achieved according to the invention by a temperature sensor which is provided in the semiconductor module and adapts the refresh time of the refresh cycle, depending on the measured semiconductor module temperature, to the retention time expected for the measured semiconductor module temperature.
With the temperature sensor for determining the temperature of the semiconductor module, that is to say in particular the DRAM, the present invention takes a completely different path from the previous concept. The refresh cycle supplied by refresh generators is no longer adapted to the highest temperature to be expected in order to ensure in all cases that the refresh time is shorter than the retention time. Rather, the actual temperature of the module is measured by the temperature sensor. The actual temperature is assigned a retention time, which, at customary or low temperatures, is always longer than the retention time at the highest temperature to be expected. The refresh cycle is then chosen in such a way that the refresh time is still just shorter than the retention time at the measured temperature. In this way, the refresh can be adapted to the actual requirement in an optimum manner in order to avoid a loss of data, which would occur if the retention time were shorter than the refresh time.
A development of the invention provides for the temperature sensor to be connected to a previously unused housing pin of the semiconductor module. However, it is also possible for the temperature sensor to be connected to an already used housing pin by a multiplexer circuit. Such an already used housing pin may be, for example, the pin for a DQ standard signal.
It has been shown that, in the case of a DRAM for example, the retention time of its memory cells is halved in the case of a temperature increase approximately every 15 to 20° K. It follows from this to a first approximation that when the chip temperature of a DRAM is reduced by 15 to 20° K., the current required for the data refresh is likewise approximately halved.
The present invention can thus improve the system performance especially at lower temperatures of distinctly below 70° C. by virtue of the refresh times that become longer or by virtue of the refresh commands that are necessary less often.
In accordance with an added feature of the invention, an access control circuit is connected to and controls the multiplexer circuit.
In accordance with an additional feature of the invention, a self-refresh oscillator and a self-refresh control circuit are connected between the temperature sensor and the self-refresh oscillator.
In accordance with a further feature of the invention, the self-refresh oscillator and the self-refresh control circuit are disposed in the semiconductor module.
In accordance with a concomitant feature of the invention, the self-refresh oscillator and the self-refresh control circuit are disposed in the control unit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor configuration with an optimized refresh cycle, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Barth Roland
Benedix Alexander
Dueregger Reinhard
Grosse Stephan
Auduong Gene N.
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Maybeck Gregory L.
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