Semiconductor configuration with a protected barrier for a stack

Details Semiconductor configuration with a protected barrier for a stack Semiconductor configuration with a protected barrier for a stack

1999-03-30

2000-03-28

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257295, 257308, 257310, H01L 2978

Patent

active

060435291

ABSTRACT:
The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.

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patent: 5923062 (1999-07-01), Ohno

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