Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-03-29
1998-06-16
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257645, 257651, H01L 2701, H01L 2358
Patent
active
057675481
DESCRIPTION:
BRIEF SUMMARY
This application is filed under 35 USC 371 of the International application PCT/EP94/03266, filed 30 Sep. 1994.
The invention relates to a semiconductor component with at least one lateral semiconductor structure with a high breakdown voltage made of a substrate, a dielectric layer adjoining the substrate, a low-doped semiconductor zone disposed on the dielectric layer and having heavily doped semiconductor zones of the semiconductor component which project into the low-doped semiconductor zone from the direction of the surface of the semiconductor component.
Such a semiconductor structure is known from the article "Extension of the Resurf Principle to Dielectrically Isolated Power Devices" of the Conference Report ISPSD 1991, Baltimore, pages 27 to 30. These are typical structures of a lateral diode on a dielectrically insulated substrate. Such structures, which are to be assigned to the general term "smart power technology", represent a connection between digital controls and power components. This technology makes the integration of logic, protective and diagnosis functions in power components possible.
An essential point of view of the mentioned technology consists in integrating several power components on a so-called semiconductor wafer, to be only called a semiconductor hereinafter, wherein the individual components are completely insulated against each other.
The mutual arrangement of logic circuits and power components in a chip is described in the article "Impact of Dielectric Isolation Technology on Power ICs" in the Conference Report ISPSD 1991, Baltimore, pages 16 to 21. The insulation required in connection with a plurality of components must be performed in such a way that the respective component is electrically insulated on all sides against the other adjoining semiconductor areas. As a rule, lateral insulation is performed in such a way that trenches are etched around the component and are subsequently filled with a dielectric. The dielectric insulation parallel with the surface of the semiconductor, i.e. in the vertical direction, is provided either by forming a pn-junction loaded in the blocking direction or by using a dielectric, for example silicon oxide. The trend is clearly toward dielectric insulation, since parasitic elements are prevented by means of this technology and, inter alia, a simpler design, along with increased interference protection, is possible.
Various methods are known for producing dielectrically insulated semiconductor wafers consisting of a substrate, a dielectric layer adjoining the substrate and a semiconductor zone disposed thereon. As known from European Laid-Open Application EP-A2 0 335 741, semiconductor wafers produced in accordance with direct connection technology are best suited for high voltage components, since they assure the best material properties of the semiconductor zone arranged on the dielectric layer.
It is further known from EO-A2 0 213 972 that it is possible to generate positive charges in the gate insulator of MOS transistors by means of ion implantation in the gate insulator, which permits the defined setting of the threshold voltage.
The maximum reverse voltages or breakdown voltages of the components which can be achieved on electrically insulated semiconductor wafers are determined, on the one hand, by the insulation capability of the "buried dielectric" and, on the other hand, by the surface properties of the surface areas in which the pn-junctions come to the surface. So-called field plates, among others, are employed in the area of the pn-junctions to prevent surface breakdowns. Otherwise a voltage breakdown is mainly limited in that the entire voltage is built up between the substrate, which as a rule is grounded, and the heavily doped areas of the semiconductor components connected to high voltage, which results in high field strengths. On the one hand, an increase in the thickness of the semiconductor zone disposed on the dielectric layer for increasing the breakdown voltage leads to considerable difficulties, since with increa
REFERENCES:
patent: 4037243 (1977-07-01), Hoffman et al.
Akio Nakagawa: "Impact of Dielectric Isolation Technology on Power ICs". In: Conference Report ISPSD 1991, Baltimore, pp. 16 to 21.
W. Wondrak et al.: "Influence of the Backgate-Voltage on the Breakdown-Voltage of SOI Power Devices". In: Electrochemical Society Proceedings, vol. 92-7, 1992, pp. 427 to 432.
Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICS, Apr. 1991, Baltimore, Maryland, pp. 27-30; Y.S. Huang et al., "Extension of Resurf Principle to Dielectrically isolated power . . . ".
Held Raban
Wondrak Wolfgang
Daimler-Benz Aktiengesellschaft
Loke Steven H.
LandOfFree
Semiconductor component with embedded fixed charges to provide i does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor component with embedded fixed charges to provide i, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor component with embedded fixed charges to provide i will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1729046