Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-09
2001-01-23
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S250000, C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S322000
Reexamination Certificate
active
06177702
ABSTRACT:
BACKGROUND ON THE INVENTION
FIELD OF THE INVENTION
The invention belongs to the semiconductor field. More specifically, the invention relates to a semiconductor component with a first and a second doped region of a second conductivity type disposed in a semiconductor substrate of a first conductivity type, and with a channel region in the semiconductor substrate between the two doped regions. In particular, the invention relates to EEPROM memory cells.
EEPROM cells (electrically erasable and programmable read-only memory cells) constitute a memory type which is growing in importance. For example, memory blocks of the FLOTOX cell type (floating gate tunnel oxide) integrated in a microcontroller environment (embedded memories) are used for smart card applications. Increasingly smaller cells are desired and required. One limiting factor is the shrinkability of the tunnel window with the associated electrical terminal region (buried channel). That limit is primarily determined by the properties of the device, as described in the following text and in my copending application entitled “Semiconductor Component with Adjustable Current Gain Based on Tunneling Current-Controlled Avalanche Breakdown” (published WO 97/38448), which is herewith incorporated by reference.
The drawing
FIG. 1
is a diagrammatic illustration of a FLOTOX type EEPROM cell. Two n-doped regions
2
,
3
form the source and drain, respectively, in a p-doped semiconductor substrate
1
. A floating gate
6
is disposed on the substrate surface lying between the source and the drain. The gate
6
is isolated from the substrate by a gate dielectric
7
and a tunnel dielectric
8
. The floating gate
6
is “connected” to the drain via the tunnel dielectric (the so-called tunnel window) and via an n-doped region
4
which is referred to as buried channel. The region underneath the gate oxide of the memory transistor, the so-called channel region
5
, is weakly p-doped. The gate dielectric
7
covers not only the channel region
5
but also an edge region
4
′ of the buried channel
4
. A control gate
9
with a terminal
10
is arranged above the floating gate
6
. The following voltages, roughly, are set for the purpose of programming:
U
controlgate
=0V
U
Drain
=+15V
U
Source
−floating
Electrons pass from the floating gate through the potential barrier in the oxide into the conduction band of the oxide and then into the substrate. This is illustrated as a band diagram in FIG.
2
. In the process, the electrons take up enough energy to produce electron-hole pairs in the substrate. (Holes tend to move along the top edge of the valence band to a higher potential—in other words upwards in the drawing—corresponding to a lower potential for holes.)
Referring now to
FIG. 3
, there is shown the potential profile along the interface perpendicularly to the drawing plane of
FIG. 2
(in other words along the axis III—III′ in
FIG. 1
) with a large lateral extent of the edge region
4
′ for different values of U
buried channel
. The pn junction between the buried channel
4
(n-doped) and the substrate (p-doped) is reverse-biased at these voltages. This leads to a large potential gradient. At the tunnel-to-gate dielectric transition, a small potential barrier Pb also forms both in the conduction band and in the valence band, since the potential at the interface depends on the thickness of the superior dielectric: the hole potential in the tunnel oxide region is higher than in the gate oxide region. The hole potential drop Pa to the p-type region does not begin until the drop in the concentration of the doping. If the level of this potential barrier is always (for holes) above the buried channel potential, holes cannot escape from the buried channel region
4
.
Referring now to
FIG. 4
, if the lateral extent of the edge region
4
′ underneath the gate dielectric
7
is insufficient, the hole potential drop Pa begins earlier. The barrier Pb lies in the falling branch and drops below the buried channel level. The holes produced by the tunneling electrons can therefore escape from the region under the tunnel dielectric
8
and traverse the hole potential gradient towards the channel region
5
. Holes are now no longer held in the buried channel region. Further electron-hole pairs are generated in the process due to collision ionization. This leads to charge multiplication, with the result that the current from the buried channel
4
to the channel region
5
, that is to say into the substrate
1
, is many orders of magnitude (10
4
to 10
6
) above the tunneling current. The charge pump for generating the programming voltage cannot deliver such a current. The cells cannot be programmed in the required time of a few milliseconds. Furthermore, the parasitic current generated by the charge multiplication loads the tunnel oxide and thus reduces the cycle stability.
The level of the potential barrier is of decisive importance for the programming operation and the electrical reliability of the component. The level of the potential barrier can be set by:
the lateral extent of the edge region
4
′;
the thickness ratio of the tunnel dielectric to the gate dielectric; and
the lateral doping profile around the gate oxide-tunnel oxide edge.
A substantial degree of lateral outdiffusion of the n-doping element (usually phosphorus) is necessary in order to obtain a sufficient extent of the edge region
4
′ underneath the gate dielectric
7
. This can be achieved by a high implantation dose. The distance between the gate oxide-tunnel oxide edge and the source region must be correspondingly large, in order that the channel length of the memory transistor does not become too short as a result of the lateral diffusion. A high buried channel concentration additionally has an unfavorable effect on the quality of the tunnel oxide. Furthermore, the sufficient extent of the edge region
4
′ is usually ensured by using two different masks to define the buried channel
4
and the tunnel window. The implantation mask for the buried channel therefore has a larger opening than the etching mask for the tunnel window.
Another way of avoiding avalanche breakdown is a large thickness ratio of the gate dielectric to the tunnel dielectric (≧4). If this ratio is to be reduced, the lateral shrink limits of the component are encountered.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor component with a split floating gate, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, in particular, provides for an EPROM having a low space requirement and high electrical reliability.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising:
a semiconductor substrate of a first conductivity type;
a first doped region of a second conductivity type formed in the semiconductor substrate, the first doped region having a surface and an edge region;
a second doped region of the second conductivity type formed in the semiconductor substrate;
a channel region disposed in the semiconductor substrate between the first and second doped regions;
a tunnel dielectric partially covering the surface of the first doped region;
a gate dielectric covering a surface of the channel region and the edge region of the first doped region;
a tunnel gate electrode having a surface disposed on the tunnel dielectric;
a channel gate electrode having a surface disposed on the gate dielectric; and
an insulation structure separating the tunnel gate electrode and the channel gate electrode at least at the surface facing the tunnel dielectric and the gate dielectric, respectively.
In accordance with an added feature of the invention, the insulation structure completely separates the tunnel gate electrode from the channel gate electrode.
In accordance with an alternative feature of the invention, the tunnel gate electrode and the channel gate
Abraham Fetsum
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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