Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-07-17
2002-04-30
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S777000, C257S783000, C257S693000
Reexamination Certificate
active
06380616
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor component which comprises at least one semiconductor chip having contact pads, a number of substrate layers, component contacts and conductor tracks which establish the electrical connection between the contact pads of the at least one semiconductor chip and the component contacts. The invention further relates to a method of producing such a semiconductor component.
Surface-mounted electronic components, also called SMD components, are usually embedded in a package of plastic molding compound from which electrical connections are brought out. There exist a large number of different types of package constructions which are of different sizes and have a different number of connections. In that configuration, a semiconductor chip is first connected to a lead frame. The semiconductor chip is usually connected to the lead frame by means of bonding, by soldering or by alloying. After the semiconductor chip has been attached, its individual connecting points are connected to the connections of the support frame, for example by means of bonding wires. After that, the semiconductor chip and the connections of the lead frame are injection-molded in such a manner that the semiconductor chip is completely encapsulated and the connections protrude from the package.
Semiconductor components must be increasingly thinner and they must be constructed with a smaller base area and less volume consumption. In the case of a storage component, the highest possible storage density is to be implemented in the smallest possible volume. There is already an ultra-thin package for storage chips, the so-called bottom-leaded plastic package (BLP). If the package space requirement is to be reduced, this can only be done by means of a much finer lead pitch in the case of a peripheral arrangement of the external leads. However, this miniaturization of the arrangement of the external leads brings one ever closer to the boundaries of processing capability, both in the production of the design and in the soldering-in on the chassis. This necessitates completely new technologies of the design, for example the multi-chip module.
In a multi-chip module, a number of semiconductor chips are placed in one plane next to one another on a substrate and are connected to the latter. In that configuration, it is possible to implement internal chip-to-chip connections. Apart from the plastic lead-frame packages, there are also ceramic packages comprising a cavity in which the semiconductor chips are inserted. There are different principles of design:
In a first form, a multi-layer wiring system (substrate) is integrated in a plastic package.
In a second form, the package includes a wiring frame system (cofired ceramic and laminate packages).
In a third, and the simplest, form the package is designed without wiring frame system. This offers the possibility of connecting the semiconductor chips directly to one another via a wire link in simple multi-chip modules having two or, at a maximum, three semiconductors.
The problem in the production of multi-chip modules is that the substrate must be produced very expensively as multi-layer wiring system. In a suitable sequence, insulating and metal layers and via holes must be placed in order to connect the chip connections to one another or, respectively, to conduct them to the outside. The current processes used in mounting the semiconductor chips are chip bonding and electrical contacting of the semiconductor chip onto the substrate, using both the wire bonding process and the flip chip method. Following this, the components are encapsulated by being sheathed with a plastic compound. In the case of ceramic packages, soldered or welded seals with a metal lid are normally used.
Apart from the complicated production of the substrate, the main disadvantage of the multi-chip modules consists in that they are not suitable for economic mass production.
U.S. Pat. No. 5,434,745 describes a semiconductor component which has a high packing density and, at the same time, requires little space by providing a module-by-module structure. There, a module consists of two substrate layers, the first substrate layer having a structured metalization on which a semiconductor chip is placed. The second substrate layer is formed with an opening instead of the semiconductor chip and is connected to the first substrate layer in a superimposed manner. An arbitrary number of modules can be connected to one another stacked on top of one another. The stack includes on two opposite outer sides semicircular via holes which are precisely above one another over all substrate layers, which holes are filled with a conductive material so that all semiconductor chips are electrically connected to one another. The stack is placed on another substrate, packaged and then provided with external component contacts.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor component with several substrate layers and one or more semiconductor chips, as well as a method of producing the semiconductor component, which overcome the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which semiconductor component has the greatest possible packaging density with the smallest possible base area. Furthermore, the component should be usable for radio-frequency applications.
With the above and other objects in view there is provided, in accordance with the invention, a vertically mountable and stacked semiconductor component, comprising:
a plurality of interconnected substrate layers lying above one another and having ends;
at least one semiconductor chip formed with contact pads disposed in an opening formed in the substrate layers;
external component contacts disposed laterally at the ends of respective substrate layers;
an electrical connection between the contact pads of the semiconductor chip and the component contacts, the electrical connection including conductor tracks of a respective substrate layer extending from an area at the semiconductor chip to the edge area of the respective substrate layer, the conductor tracks of a substrate layer having a substantially equal length; and
the electrical connection being configured to define a signal delay of substantially equal length between each contact pad of the semiconductor chip to an associated the component contact.
There is also provided, in accordance with the invention, a method of producing the vertically mounted and stacked semiconductor component. The method comprises the following steps:
providing a first layer of a two-layer substrate material with a plurality of substantially equal-length conductor tracks and a second layer of the two-layer substrate with at least one opening, the conductor tracks ending on one side of the substrate layer for placing external component contacts;
placing at least one semiconductor chip in the at least one opening;
connecting the at least one semiconductor chip to the first substrate layer;
electrically contacting the at least one semiconductor chip with the conductor tracks; and
placing a further substrate layer without conductor tracks and openings on the two-layer substrate material and covering the second layer with the opening.
Furthermore, there is provided a method of producing a semiconductor component with plug contacts, which comprises the following steps:
providing a first layer of a two-layer support material with substantially equal-length conductor tracks, and a second layer of the two-layer support material with an opening, the conductor tracks being structured between the two layers, the first layer having an elongated side provided with metalization contacts and mechanical coding;
placing at least one semiconductor chip into the opening;
connecting the at least one semiconductor chip to the first substrate layer;
electrically contacting the at least one semiconductor chip with the
Neu Achim
Tutsch Günter
Clark Jhihan B
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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