Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-10-29
2004-08-31
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S691000, C257S692000, C257S696000, C257S784000
Reexamination Certificate
active
06784525
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to a semiconductor package having a multi layered leadframe, to a method for fabricating the package, and to systems incorporating the package.
BACKGROUND OF THE INVENTION
Semiconductor packages, particularly chip scale packages, are being manufactured with a smaller outline and with a higher pin count than conventional plastic or ceramic packages. A chip scale package includes a semiconductor die, and terminal contacts for surface mounting the package to a supporting substrate, such as a circuit board or module substrate. The terminal contacts typically comprise balls, bumps or pins, arranged in a dense area array, such as a ball grid array (BGA), or a pin grid array (PGA). Chip scale packages can also include an encapsulant which at least partially encapsulates the die and electrical connections with bond pads on the die.
Different methods are employed in the industry for fabricating chip scale packages. One conventional method uses a rigid substrate, such as a reinforced polymer laminate, attached to the die in a chip on board (COB) or a board on chip (BOC) configuration. The substrate includes conductors, such as copper traces, that are wire bonded to the bond pads on the die. The substrate can also include bonding sites in electrical communication with the conductors for mounting the terminal contacts in the required area array.
Another method for fabricating chip scale packages employs a flexible interposer, similar to TAB tape, which includes conductors configured for bonding directly to the bond pads on the die. The flexible interposer can also include bonding sites for the terminal contacts.
Yet another method for fabricating chip scale packages uses a metal leadframe that is attached and wire bonded to the die. The metal leadframe includes leads which provide bonding sites for the wire bonds to the die, and the terminal contacts for the package. A lead on chip leadframe includes leads that are also adhesively attached to the face of the die.
Each of these fabrication methods has advantages and disadvantages. One advantage of packages formed with rigid substrates, and with flexible interposers, is that fine pitch standards can be employed. Standard setting bodies for the semiconductor industry, such as JEDEC and EIAJ, set the pitch standards for semiconductor packages. In general the “pitch” of the terminal contacts on a package is the center to center spacing between adjacent terminal contacts. Currently, the finest pitch standard employed for BGA packages is 0.50 mm, but finer pitches are anticipated.
In order to achieve these fine pitch standards, design rules on the width and the spacing of the conductors for the terminal contacts are employed. These design rules are sometimes referred to as line/space rules. Currently, rigid substrates can include conductors having a width and spacing as small as about 50 &mgr;m. Flexible interposers can include conductors having a width and a spacing as small as about 35 &mgr;m. In contrast, the leads on metal leadframes can be made with a width and a spacing of only about 80 &mgr;m for etched leadframes, and a width and a spacing of only about 70 &mgr;m for stamped leadframes.
Besides finer pitches, another advantage of rigid substrates and flexible interposers over leadframes, is that ground and power planes can be employed for grounding and powering, or for adjusting the impedance of selected terminal contacts on the packages. In addition, both rigid substrates and flexible interposers can be used with different bond pad configurations such as center line patterns, T patterns or I patterns. In contrast, metal leadframes typically do not include ground and/or power planes, and are employed mostly with center line patterns of bond pads.
Despite these disadvantages metal leadframes still possess some advantages. In particular, metal leadframes are less expensive to manufacture than rigid substrates and flexible interposers. In addition, conventional packaging equipment such as wire bonders, die attachers, conveyors and magazines can be employed with metal leadframes. Accordingly packages can be made cheaper and more reliably with Metal leadframes than with rigid substrates and flexible interposers.
The present invention is directed to a semiconductor package constructed with a metal leadframe that is able to accommodate finer line/space design rules than conventional stamped or etched metal leadframes. In addition, the leadframe can include a ground and/or power plane, and can accommodate dies having different patterns of bond pads including T patterns and I patterns.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved semiconductor package, a method for fabricating the package, and electronic systems incorporating the package are provided.
The package includes a semiconductor die having a circuit side, an opposing back side and a pattern of bond pads on the circuit side. The package also includes a multi layer leadframe attached and wire bonded to the die, a pattern of terminal contacts on the multi layer leadframe, and a plastic body encapsulating the die and the leadframe. The multi layer leadframe includes a first leadframe and a second leadframe attached to the first leadframe.
The first leadframe includes a plurality of first leads (circuit side leads) attached to the circuit side of the die and having bonding sites wire bonded to the die. The first leads also include pads arranged in an area array and configured for bonding the terminal contacts thereto. The second leadframe includes a plurality of second leads (back side leads) having bonding sites located proximate to the backside of the die and connecting segments attached to the first leads. The wire bonding sites on the second leads are located outside of the periphery of the die to provide access for wire bonding.
The leads form the internal lead system for the package, and provide electrical paths between the die and the terminal contacts for the package. In addition, the second leads can be configured to provide electrical paths to selected terminal contacts that would otherwise be non-accessible due to line/space design limitations. The second leads can also be configured to provide a ground and/or power plane for the package.
The method for fabricating the package includes the steps of attaching the first leads to the circuit side of the die, and then attaching the second leads to the first leads. In addition, the method includes the step of wire bonding wires to the bond pads on the die and to the bonding sites on the leads. The method also includes the steps of forming the plastic body, and forming the terminal contacts on the pads of the first leads.
The package can be used to construct electronic systems such as modules, circuit boards, systems in a package (SIP) and computers.
REFERENCES:
patent: 5237202 (1993-08-01), Shimizu et al.
patent: 5710695 (1998-01-01), Manteghi
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6054754 (2000-04-01), Bissey
patent: 6075283 (2000-06-01), Kinsman et al.
patent: 6130473 (2000-10-01), Mostafazadeh et al.
patent: 6184574 (2001-02-01), Bissey
patent: 6218216 (2001-04-01), Corisis
patent: 6229202 (2001-05-01), Corisis
patent: 6246110 (2001-06-01), Kinsman et al.
patent: 6285560 (2001-09-01), Lyne
patent: 6303981 (2001-10-01), Moden
patent: 6303985 (2001-10-01), Larson et al.
patent: 6310388 (2001-10-01), Bissey
patent: 6310390 (2001-10-01), Moden
patent: 6387732 (2002-05-01), Akram
patent: 6391687 (2002-05-01), Cabahug et al.
patent: 6429528 (2002-08-01), King et al.
patent: 6451624 (2002-09-01), Farnworth et al.
patent: 6501165 (2002-12-01), Farnworth et al.
patent: 6506625 (2003-01-01), Moden
patent: 6552427 (2003-04-01), Moden
patent: 6589810 (2003-07-01), Moden
Rao R. Tummala and Eugene J. Rymaszewski, Microelectronics Packaging Handbook, 1989, pp. 578-586, Van Nostrand Reinhold, New York.
Hui Chong Chin
Kuan Lee Choon
Lai Lee Wang
Gratton Stephen A.
Micro)n Technology, Inc.
Tran Thien F
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