Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-08-14
2001-11-06
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C324S1540PB
Reexamination Certificate
active
06313655
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor component and a method for testing and operating a semiconductor component, which has an electronic circuit which is formed on a main surface of a semiconductor chip, and has connecting surfaces (“pads”), which are arranged on the main surface of the semiconductor chip and are electrically coupled to the electronic circuit, for electrical communication between the circuit and the outside world, the electronic circuit on the one hand being operable in a test mode, which can normally be carried out in the wafer composite of the semiconductor chips and in which an externally supplied test signal is applied to a predetermined pad, and on the other hand being operable in an operating mode in which operating signals are applied to the pads and/or to terminal pins which are electrically coupled to the pads and are connected to the outside of the component.
As an example of such a semiconductor component, a synchronous dynamic semiconductor memory (SDRAM) has become known, for example, from Y. Takai et al., “250 Mbyte/s Synchronous DPAM Using a 3-Stage-Pipeline Architecture,” IEEE Journal of Solid-State Circuits, Vol. 29, April 1994, p. 526; Yuno Choy et al., “16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate,” IEEE Journal of Solid-State Circuits, Vol. 29, April 1994, p. 529. According to JEDEC Standard No. 21-C, such SDRAM semiconductor memories are available in so-called TSOP-2 housings with, typically, 50 external terminal pins (1 M×16 SDRAM, 1 M×18 SDRAM, 256 k×16 SDRAM) or 54 terminal pins (16 M×4 SDRAM, 8 M×8 SDRAM, 4 M×16 SDRAM). Metallic pads are formed predominantly in an edge region on the main surface of the semiconductor chip. The pads are used for electrical communication between the circuit components that are formed on the semiconductor chip and the outside world, and typically have a square shape with dimensions of several &mgr;m×&mgr;m. During installation in the semiconductor component housing, some of these pads are connected, for example via bonding wires, to the terminal pins which project to the exterior. After installation of the semiconductor component in the housing, a relatively small number of the pads are no longer accessible from the exterior. They are required only in the test mode, in which the semiconductor chips, not yet in their housing, are still in the wafer composite.
FIG. 2
shows schematically those components of a conventional synchronous dynamic semiconductor memory SDRAM which are required to explain the problem on which the invention is based. The illustration shows the pads
1
and
2
which are assigned to the two DQM terminals LDQM (lower input mask/output enable) and UDQM (upper input mask/output enable) of the SDRAM. The pads are metallic pads, essentially having a square shape. They are disposed on the main surface of the semiconductor chip and are electrically connected via lines
3
,
4
and via drivers
5
,
6
to the control and logic circuit arranged in the semiconductor chip (indicated in
FIG. 2
by the designations LDQM internal and UDQM internal). Furthermore, a test pad
7
is provided, which is required for test purposes, and to which a test activation signal EXTADDR is applied externally in the test mode. The actual test mode sequences in the form of so-called IPL codes (which are used, inter alia, to test to a greater extent the functionality of the redundant and non-redundant bit lines when the word line and the like are open of the semiconductor memory which is still located in the wafer composite, that is to say has not yet been canned) are supplied from a control circuit
9
in the form of a signal TMEXTADDR. The signal TMEXTADDR is applied to one input of an AND gate
10
, at whose output a signal Ax is output. The output signal Ax is used to test the relevant circuit parts. The test mode is activated by the test activation signal EXTADDR which is applied externally to the test pad
7
, is applied via a driver
8
to the second input of the AND gate
10
, and controls the control circuit
9
, and thus the emitted test mode sequences, in the sense of switching them on and off. The metallic test pad
7
which is formed on the main surface of the semiconductor chip is thus required only for test purposes, and is actually no longer required subsequently.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor component (in particular, a synchronous dynamic semiconductor memory of the random access type) and a method of testing and operating a semiconductor component, which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type wherein it is possible to do away with test pads that are required only for test purposes but occupy valuable chip area.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising:
a semiconductor chip having a main surface and a plurality of terminal pins;
an electronic circuit formed in or on the main surface of the semiconductor chip and connected to the terminal pins;
connecting surfaces disposed on the main surface of the semiconductor chip and electrically connected to the
electronic circuit for electrically communicating with the electronic circuit from outside the semiconductor chip;
the electronic circuit being operable in a test mode, in which an external test signal is applied to a predetermined one of the connecting surfaces, and in an operating mode, in which operating signals are applied to one of the connecting surfaces and the terminal pins coupled to the connecting surfaces; and
a switching device connected to at least one of the connecting surfaces, the switching device switching a function of the at least one connecting surface from the test mode to the operating mode.
In accordance with an added feature of the invention, the switching device is hard-wired on the main surface of the semiconductor chip.
In accordance with an additional feature of the invention, the switching device irreversibly switches the at least one connecting surface to the operating mode.
In accordance with another feature of the invention, the semiconductor component includes a data input/output, and the at least one connecting surface is assigned to the data input/output.
In accordance with a further feature of the invention, the switching device is connected to and switched by a control signal originating from a control circuit.
In accordance with again an added feature of the invention, the semiconductor component is a synchronous, dynamic semiconductor memory component of random access type, and wherein the connecting surfaces are an LDQM and a UDQM pad, respectively, and wherein the switching device functionally changes one of the LDQM and UDQM pads to a test mode.
In accordance with again an additional feature of the invention, the one LDQM pad and UDQM pad is switched by the switching device as an “Extended Address Bit” in the test mode.
With the above and other objects in view there is also provided, in accordance with the invention, a method of testing and operating the semiconductor component, wherein the semiconductor component has an electronic circuit which is formed in or on a main surface of a semiconductor chip, connecting surfaces disposed on the main surface of the semiconductor chip and electrically connected to the electronic circuit, for external electrical access to the electronic circuit, and terminal pins electrically connected to the connecting surfaces and connected to an exterior of the component, the method which comprises:
selectively operating the electronic circuit in a test mode, in which an external test signal is applied to a predetermined connecting surface, and in an operating mode, in which operating signals are applied to at least one of the connecting surfaces and the terminal pins of the component; and
connecting a switching device to at least one pad whereby it is possible
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Metjahic Safet
Stemer Werner H.
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