Semiconductor component and method for precluding...

Semiconductor device manufacturing: process – Direct application of electrical current – Electromigration

Reexamination Certificate

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C438S618000, C438S622000

Reexamination Certificate

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07026225

ABSTRACT:
A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.

REFERENCES:
patent: 5517062 (1996-05-01), Lur et al.
patent: 5739587 (1998-04-01), Sato
patent: 6245996 (2001-06-01), Atakov et al.
patent: 6559499 (2003-05-01), Alers et al.
patent: 2001/0001427 (2001-05-01), Atakov et al.
Ogawa, E.T., et al., Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads.

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