Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-05-13
2001-02-13
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C326S034000
Reexamination Certificate
active
06188246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sequential circuit which has a function of holding data in a sleep mode.
2. Description of the Related Art
Semiconductor integrated logic circuits are commonly provided with a system including a transistor circuit which makes a high speed operation in an active mode and low power consumption in a sleep mode possible. In particular, the system has a data holding function for protecting stored data in a sequential circuit from being destroyed during a sleep mode. For example, in Japanese Patent No. 2631335 is disclosed the technique of making a high speed operation possible and of supplying electric power via transistors with higher threshold voltages to shut off a leakage current in the sleep mode. Especially, the technique of a sequence circuit is disclosed in which the electric power is directly supplied and a bi-directional circuit composed of higher threshold voltage transistors is added to shut off the leakage current in the sleep mode and to simultaneously protect stored data from being destroyed.
FIG. 1
is a circuit diagram illustrating a conventional semiconductor integrated logic circuit including a sequential circuit, which has a function of holding data in the sleep mode. As shown in
FIG. 1
, a control transistor HP
1
I of a p-channel MOSFET of a higher threshold voltage is connected at its source electrode to a higher potential side actual power supply line VDD and at its drain electrode to a higher potential side quasi power supply line VDDV. In response to a sleep mode switching signal SL received at its gate electrode, the control transistor HP
1
I electrically connects or disconnects the higher potential side actual power supply line to and from the quasi power supply line. Also, another control transistor HN
1
I of an n-channel MOSFET of a higher threshold voltage is connected at its source electrode to a low potential side actual power supply line GND and at its drain electrode with a lower potential side quasi power supply line GNDV. In response to an inverted sleep mode switching signal SLB received at its gate electrode, the control transistor HN
1
I electrically connects or disconnects the lower potential side actual power supply line to and from the quasi power supply line. The inverted sleep mode switching signal SLB is a signal obtained by inverting the sleep mode switching signal SL. The sleep mode switching signal SL and inverted sleep mode switching signal SLB are supplied from a sleep mode control circuit (not shown).
A CMOS circuit section composed of lower threshold voltage transistors includes inverter circuits INV
1
I and INV
2
I. More particularly, each of the inverter circuits INV
1
I and INV
2
I is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The gate electrodes of the two transistors are connected to each other as a common input terminal and the drain electrodes of the same are connected to each other as a common output terminal. The source electrodes of the lower threshold voltage p-channel MOSFETs in the inverter circuits INV
1
I and INV
2
I are connected to the higher potential side quasi power supply line VDDV. The source electrodes of the lower threshold voltage n-channel MOSFETs in the inverter circuits INV
1
I and INV
2
I are connected to the lower potential side quasi power supply line GNDV.
A latch circuit
10
shown in
FIG. 1
will be now explained. The CMOS latch circuit
10
is composed of higher threshold voltage transistors, two transfer gates TM
1
and TM
2
, three inverter circuits INV
1
, INV
2
, and INV
3
, and two higher threshold voltage control transistors HP
1
and HN
1
for shutting off sub-threshold leakage currents.
The inverter circuit INV
1
performs buffering of a data signal D supplied to the latch circuit
10
and is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The gate electrodes of the two transistors are connected to each other as a common input terminal for receiving the data signal D and the drain gates of the same connected to each other as a common output terminal.
The control transistor HP
1
is composed of a p-channel MOSFET of a higher threshold voltage and is connected at its source electrode to the higher potential side actual power supply line VDD. In response to the sleep mode switching signal SL received at its gate electrode, the switching of the control transistor HP
1
is controlled. The control transistor HN
1
is composed of an n-channel MOSFET of a higher threshold voltage and is connected at its source electrode to the lower potential side actual power supply line GND. In response to the inverted sleep mode switching signal SLB received at its gate electrode, the switching of the control transistor HN
1
is controlled. The source electrode of the lower threshold voltage p-channel MOSFET of the inverter circuit INV
1
is connected to the drain electrode of the control transistor HP
1
. Similarly, the source electrode of the lower threshold voltage n-channel MOSFET of the inverter circuit INV
1
is connected to the drain electrode of the control transistor HN
1
.
The transfer gate TM
1
is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The source electrode of one transistor is joined to the drain electrode of the other, forming a parallel connection. One of the two joints is connected an output terminal of the inverter circuit INV
1
and the other serves as an output of the latch circuit
10
for outputting a latch output signal QB to the succeeding stage.
A clock signal &phgr; is applied to the gate electrode of the lower threshold voltage n-channel MOSFET of the transmission circuit TM
1
while an inverted clock signal *&phgr; which is an inverted form of the clock signal &phgr; is applied to the gate electrode of lower threshold voltage p-channel MOSFET.
The transfer gate TM
2
is substantially identical in the circuitry construction to the transfer gate TM
1
and connected at one of its bi-directional electrodes to the input terminal of the inverter circuit INV
3
and at the other to the output terminal of the inverter circuit INV
2
. The transfer gate TM
2
may be composed of MOSFETs of either a low or a higher threshold voltage.
The inverter circuits INV
2
and INV
3
are substantially identical in the circuitry construction to the inverter circuit INV
1
. While the inverter circuit INV
1
is composed of the lower threshold voltage MOSFETs, higher threshold voltage MOSFETs are used in the inverter circuits INV
2
and INV
3
. The inverter circuit INV
3
receives the latch output signal QB of the latch circuit
10
as an input signal, unlike the inverter circuit INV
1
. The inverter circuit INV
3
is connected directly between the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND, without passing through the control transistor HP
1
as the higher threshold voltage p-channel MOSFET and the control transistor HN
1
as the higher threshold voltage n-channel MOSFET. The output of the inverter circuit INV
3
is connected to the input of the inverter circuit INV
2
. The inverter circuit INV
2
, like the inverter circuit INV
3
, is corrected directly between the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND.
The operation of the latch circuit
10
shown in
FIG. 1
will be described as a sequential circuit having a function of holding data in the sleep mode.
In particular, the inverted data signal D produced by the inverter circuit INV
1
is taken at the timing of the clock signal &phgr; and the inverted clock signal *&phgr; supplied to the transfer gate TM
1
and outputted as the output QB of the latch circuit
10
to the succeeding stage. The inverted data signal from the inverter circuit INV
1
is received by the transfer gate TM
1
only when the sleep mode switching signal SL and
Le Thong
NEC Corporation
Nelms David
Sughrue Mion Zinn Macpeak & Seas, PLLC
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