Semiconductor circuit with mask register

Details Semiconductor circuit with mask register Semiconductor circuit with mask register

2008-06-17

2008-06-17

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C327S108000, C327S143000

Reexamination Certificate

active

07389437

ABSTRACT:
A semiconductor circuit includes an integrated circuit having a backup area that is constantly powered and a power-off area that is powered off in a standby mode. A register in the power-off area stores a mask signal that is normally set to the high level but is changed to the low level before a transition to the standby mode. A latch circuit in the backup area latches the low level but not the high level of the mask signal. A masking circuit in the backup area masks input signals from the power-off area to the backup area while the latch circuit is in the latched state. Besides preventing erratic input to the backup area during normal-to-standby transitions, this arrangement prevents leakage of current from the backup area to the power-off area on the mask signal line in the standby mode.

REFERENCES:
patent: 6411564 (2002-06-01), Ikeda
patent: 6734706 (2004-05-01), Yoshida et al.
patent: 6894545 (2005-05-01), Kodama
patent: 7239187 (2007-07-01), Ishikawa
patent: 2002-223156 (2001-01-01), None
patent: 2002-312073 (2002-10-01), None

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