Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-04
2004-04-27
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06728943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit extraction apparatus, an autoplacement/routing apparatus, their methods and a library distribution system for designing a semiconductor integrated circuit by combining a plurality of cells pre-registered in a cell library.
2. Description of the Prior Art
FIG. 4
is a diagram depicting the layout of a yet-to-be placed and routed discrete cell, and
FIG. 5
is a diagram showing the layout of the cell after placement/routing by the conventional autoplacement/routing apparatus.
In
FIGS. 4 and 5
, reference numeral
101
denotes a semiconductor substrate;
102
denotes a diffused layer;
103
denotes poly-silicon wiring;
104
denotes first layer wiring formed of metal such as aluminum (Al);
105
denotes first contacts for connecting the diffused layer
102
and the first layer wiring
104
;
106
denotes second contacts for connecting the poly wiring
103
and the first layer wiring
104
; and
107
second layer wiring formed of metal such as aluminum. The first and second contacts are formed on first and second interlayer insulating films (not shown), respectively.
The operation of the above prior art example will be described below in brief.
In the first place, the parasitic capacitance between respective wiring conductors in the cell is extracted by a semiconductor circuit extraction apparatus to compute delays in the signal propagation from the input to output of the cell, and the delay information thus obtained is stored as library data for subsequent autoplacement/routing in a cell library. Then, the yet-to-be placed and routed discrete cell (
FIG. 4
) is prepared, on which the autoplacement/routing apparatus carries out required conductor placement/routing in accordance with the delay information stored in the cell library.
In this instance, the prior art computes the delay time based solely on the parasitic capacitance between the wiring conductors of the cell without regard to the influence of wiring conductors that might be routed across the cell surface afterward.
Accordingly, when the wiring conductors extending across the cell surface (which wiring will hereinafter be referred to as cell-top wiring conductors) are present after the conductor placement/routing, the actual delay time becomes longer than the delay time stored in the cell library due to parasitic capacitances between the cell-top wiring conductors and the wiring conductors in the cell (which wiring will hereinafter be referred to as intra-cell wiring conductors); that is, the prior art has a defect that the delay computation based on the prestored library data underestimates the delay time.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor circuit extraction apparatus, an autoplacement/routing apparatus, their methods and a library distribution system that permit accurate computation of the delay time as data for placement/routing in accordance with parasitic capacitances between the cell-top wiring conductors and the intra-cell wiring conductors.
The semiconductor circuit extraction apparatus according to an aspect of the present invention comprises: means for detecting the uppermost wiring layer of the cell; and means for virtually routing a wiring conductor on every wiring track of a cell-top wiring layer directly overlying the uppermost wiring layer of the cell and for extracting parasitic capacitances of the virtually routed wiring conductors as well as all the internal wiring conductors of the cell.
According to another aspect of the invention, the parasitic capacitance extracting means forms or generates a wiring conductor of the minimum line width defined by design rules on each of wiring tracks spaced apart a distance defined by the autoplacement/routing apparatus in the cell-top wiring layer directly overlying the uppermost wiring layer of the cell.
According to another aspect of the invention, the capacitance extracting means provides, as library data, delay information derived using the extracted parasitic capacitances.
The autoplacement/routing apparatus according to another aspect of the present invention comprises placement means, global routing means, detailed routing means and additional routing means. The placement means, the global routing means and the detailed routing means are driven in this order. Subsequent to detailed routing by the detailed routing means, the additional routing means inputs information about the uppermost wiring layer of the cell and performs additional wiring conductor routing on blank tracks in a virtual cell-top wiring layer.
According to another aspect of the invention, the autoplacement/routing apparatus obtains the information about the uppermost wiring layer of the cell from the uppermost wiring layer detecting means of the semiconductor circuit extraction apparatus.
According to another aspect of the invention, the additional routing means retrieves wiring tracks in the cell-top wiring layer directly overlying the uppermost wiring layer based on the information about the uppermost wiring layer, then stores wiring grids with no wiring element, and forms or generates wiring conductors connecting the stored wiring grids.
The autoplacement/routing method according to another aspect of the present invention comprises the steps of: registering in a cell library, as cell data, information indicating the virtually routed cell-top wiring layer directly overlying the uppermost wiring layer of the cell, together with delay information derived using extracted parasitic capacitances of all the wiring conductors including those virtually routed wiring conductors of the cell-top wiring layer; offering the cell library with the registered data; and reading out the registered information from the cell library and inputting it to the autoplacement/routing apparatus.
According to another aspect of the invention, the autoplacement/routing apparatus further comprises an additional routing step of routing additional wiring conductors on blank tracks in the virtually routed cell-top wiring layer directly overlying the uppermost wiring layer of the cell after detailed routing.
The semiconductor circuit extraction method according to another aspect of the invention comprises the steps of: virtually routing wiring conductors on all tracks of the cell-top wiring layer directly overlying the uppermost wiring layer of the cell; and extracting the parasitic capacitances of all the wiring conductors including those virtually routed conductors of the cell-top wiring layer.
The library distribution system according to another aspect of the present invention comprises: means for registering in a cell library, as cell data, information indicating the virtually routed cell-top wiring layer directly overlying the uppermost wiring layer of the cell, together with delay information derived using extracted parasitic capacitances of all the wiring conductors including those virtually routed wiring conductors of the cell-top wiring layer; means for offering the cell library with the registered data to a customer; and means for reading out the registered information from the cell library and for inputting it to the autoplacement/routing apparatus on the part of the customer.
According to still another aspect of the present invention, the library distribution system further comprises additional routing means for routing additional wiring conductors on blank tracks in the virtually routed cell-top wiring layer directly overlying the uppermost wiring layer of the cell after detailed routing.
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Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Thompson A. M.
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