Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-17
2003-02-18
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S342000, C257S361000, C257S140000, C257S173000, C361S100000, C361S111000, C361S056000
Reexamination Certificate
active
06521951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device and, more particularly, to a semiconductor circuit device having an input protection circuit protecting an input circuit against a surge voltage such as static electricity applied to an input pad. More specifically, the present invention relates to a structure for improving surge resistance of a multipower source semiconductor circuit device to which a plurality of power supply voltages are applied externally.
2. Description of the Background Art
FIG. 1
schematically shows a configuration of an signal input portion of a conventional semiconductor circuit device. Referring to
FIG. 1
, the conventional semiconductor circuit device includes an input circuit
2
receiving a signal applied to input pad
1
and generating an internal signal, and an internal circuit
3
performing a prescribed process in accordance with the internal signal applied from input circuit
2
. Input circuit
2
operates using a power supply voltage Vddi on a power supply node PS
1
and the ground voltage GND as two operational power source voltages, and converts an amplitude of the input signal applied to input pad
1
to the level of the power supply voltage Vddi. Internal circuit
3
operates using a power supply voltage Vdd on a power supply node PS
2
and the ground voltage GND as two operational power source voltages.
The semiconductor circuit device further includes a diode type input protection circuit
2
for protecting input circuit
2
against a surge voltage applied to input pad
1
. Diode type input protection circuit
4
includes a PN junction diode D
1
connected in the forward direction between an internal node
5
and a power supply node PS
3
, and a PN junction diode D
2
connected in reverse direction between internal node
5
and the ground node. Power supply node PS
3
of diode type input protection circuit
4
and power supply node PS
1
of input circuit
2
are connected to each other through a power supply line
6
. A parasitic capacitance C
1
is parasitically connected to power supply line
6
, and there is a parasitic capacitance C
2
on a power supply line
7
connected to power supply node PS
2
. Power supply lines
6
and
7
are separated from each other. When an input signal having relatively small amplitude such as an LVTTL (low voltage transistor-transistor-logic) is used as an input signal, power supply voltage Vddi for the input circuit is set at a value lower with respect to the power supply voltage Vdd of the internal circuitry. When the power supply voltage Vdd is 3.3 V, LVTTL has input high level voltage VIH of 2.0 V and an input low level voltage VIL of 0.8 V. In order to accurately determine the H and L levels of such a signal having small amplitude, the voltage level of power supply voltage Vddi of input circuit
2
is made lower than the power supply voltage Vdd of the internal circuitry.
Input circuit
2
is an input buffer circuit connected to input pad
1
, of which total number is relatively small, and hence capacitance value of parasitic capacitance C
1
connected to power supply line
6
is relatively small. In contrast, internal circuit
3
connected to power supply line
7
has a number of components, and capacitance value of parasitic capacitance C
2
connected to internal power supply line
7
is relatively large.
Assume that a positive surge voltage is applied to input pad
1
. The positive surge voltage is at a voltage level sufficiently higher than power supply voltage Vddi, so that diode D
1
is rendered conductive and the surge voltage is transmitted from power supply node PS
3
through power supply line
6
and power supply node PS
1
to input circuit
2
. The surge voltage is dissipated and consumed by the components included in input circuit
2
, and the surge voltage is absorbed.
When the surge voltage is to be absorbed by power supply line
6
, however, the surge voltage cannot entirely be absorbed by parasitic capacitance C
1
as the capacitance value of parasitic capacitance C
1
connected to power supply line
6
is small, and a high surge voltage is undesirably applied to the components of input circuit
2
, damaging the components (transistors) included in input circuit
2
.
Similarly, when a negative surge voltage generates on input pad
1
, diode D
2
is rendered conductive, and the negative surge voltage is absorbed by the ground line through the ground node of diode type input protection circuit
4
. When the ground node of diode type input protection circuit
4
and the ground node of input circuit
2
are connected to each other by the ground line, the negative surge voltage cannot sufficiently be absorbed as the parasitic capacitance of the ground line is also small, and therefore, components of input circuit
2
are damaged by the negative surge voltage.
Therefore, even when input protection circuit
4
is provided, the surge voltage cannot effectively be absorbed, and hence input circuit
2
cannot sufficiently be protected against the surge voltage.
FIG. 2
shows another configuration of the conventional input protection circuit. In the configuration shown in
FIG. 2
, a PN junction diode D
3
is connected in the forward direction between power supply line
6
of input circuit
2
and power supply line
7
of internal circuit
3
. In the configuration shown in
FIG. 2
, when a positive surge voltage is applied, diode D
1
is rendered conductive and the surge voltage is transmitted to power supply line
6
. When the surge voltage cannot sufficiently be absorbed by parasitic capacitance C
1
, diode D
3
is rendered conductive, the surge voltage is transmitted from power supply line
6
to power supply line
7
, and the surge voltage is absorbed by parasitic capacitance C
2
existing on power supply line
7
. As internal circuit
3
has a number of components and parasitic capacitance C
2
has large capacitance value, the surge voltage can be absorbed without damaging the components of internal circuit
3
.
By connecting separately provided power supply lines
6
and
7
utilizing diode D
3
, absorbing path of the positive surge voltage is ensured, improving surge resistance. By providing similar configuration, a negative surge voltage absorbing path can also be formed for the negative surge voltage.
FIG. 3
is a schematic diagram representing a cross sectional structure of PN junction diode D
3
shown in FIG.
2
. Referring to
FIG. 3
, PN junction diode D
3
includes an N well
11
formed at a surface of a P type semiconductor substrate
10
, a high concentration P type impurity region
12
formed at a surface of N well
11
, and a high concentration N type impurity region
13
formed spaced from impurity region
12
at the surface of N well
11
.
Diode D
3
utilizes a PN junction formed between P type impurity region
12
and N well
11
. P type impurity region
12
is connected to power supply node PS
1
applying power supply voltage Vddi, and impurity region
13
is connected to power supply node PS
2
applying power supply voltage Vdd. N well
11
has low impurity concentration and relatively high resistance. The PN junction between P type impurity region
12
and the N well is connected in series with a well resistance R of N well
11
. When the surge voltage is transmitted from input pad
1
through diode D
1
and power supply line
6
to diode D
3
, it is necessary to transmit the surge voltage at high speed to power supply node PS
2
using diode D
3
, so that the surge voltage is absorbed at high speed by parasitic capacitance C
2
of power supply line
7
connected to power supply node PS
2
.
However, as well resistance R has high resistance value, the surge voltage cannot fully be transmitted from power supply node PS
1
to power supply node PS
2
(as there is a considerable voltage drop caused by well resistance R), and therefore the voltage level of the surge voltage at power supply node PS
1
cannot sufficiently be lowered. Therefore, there is a case that a large surge voltage is applied to input ci
Ohbayashi Shigeki
Sato Hirotashi
Clark Jasmine J B
McDermott & Will & Emery
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