Semiconductor circuit device having multiplex selection function

Details Semiconductor circuit device having multiplex selection function Semiconductor circuit device having multiplex selection function

1991-05-31

1993-07-13

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

365200, 36523006, 36523008, 371 103, G11C 800

Patent

active

052279979

ABSTRACT:
The semiconductor circuit device includes a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second column decoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signal. The second column decoder selects the same column in a duplicated way in response to different column select signals. Since the same column is selected in a duplicate way by the different column select signals, it will be possible to simultaneously select a desired combination of a plurality of columns. A combination of a plurality of columns simultaneously selected can be arbitrarily set and a desired combination of columns can be selected with a simplified circuit structure at high speed. It will be possible to repair a column containing a defective bit without providing a redundant column by providing an input/output control circuit for further selecting a column from the columns simultaneously selected in accordance with the column select signal.

REFERENCES:
patent: 3652841 (1972-03-01), Lanning
patent: 4176287 (1979-11-01), Remedi
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 4914632 (1990-04-01), Fujishima et al.
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six-Transistor Cell, by Kiyofumi Ochii, et al., pp. 798-803.
1982 IEEE International Journal of Solid-State Circuits Conference, 1982 Digest of Technical Papers, Oct. 1982 vol. SC-17, No. 5, 32K and 16K Static MOS RAMs Using Laser Redundancy Techniques, by Richard J. Smith, et al., pp. 252-253.
LSI Handbook, 1984, pp. 100-101, 3-25.

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