Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2002-03-27
2003-09-23
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S296000, C257S443000
Reexamination Certificate
active
06624492
ABSTRACT:
CROSS REFERENCE RELATED APPLICATIONS
This application claims the benefit of priority from prior Japanese Patent Application P2001-90461 filed on Mar. 27, 2002; the contents of which are incorporated by reference herein.
FIELD OF THE INVENTION
The present invention relates to a gate array type semiconductor integrated circuit having so-called IP (IP: Intellectual Property) and a manufacturing method of the same.
BACKGROUND OF THE INVENTION
Recent ASIC (Application Specific Integrated Circuit) products is have increased processing speed as well as increased circuit size. LSIs have a large scale and can be fabricated in a large scale, in the system design, the design of formality for well used circuits is standardized, and a product specification as IP, which describes a function and a performance, and a circuit constitution are determined.
Since any IP obtained market advantage, for improved performance, designers look the most advanced semiconductor process technology. Although the system design in a realized with dedicated LSI storing the IP, the demand of system designers to use the IP in ASIC products becomes significant when the IP is generalized. This is because the LSIs are collectively integrated on one chip by adopting the ASIC. Thus lessening the number of parts and allowing microfabrication and low cost.
Dmands of users using the ASIC increases and further realization of circuits which are low in cost and show a high speed operation and high performance comes to be desired. The ASIC may inclined an embedded array and a standard. Since the IP is often the most advanced product that can be realized by use of the, difficulty of realization with the ASIC occurs. For example, the difficulty is a high speed operation of a large scale circuit. In the gate array, a wafer in which transistors are arranged regularly is first prepared, and Al wirings connecting the transistors respectively are connected so as to meet the demands of customers. However, when it is intended to realize a large scale circuit, many gate scales are necessary, and the circuit itself becomes large. The wiring in the large scale circuit IP becomes long due to the large circuit, and high speed operation becomes difficult.
An embedded array and a standard cell may also be used. These methods are the same as that to design individual LSIs in accordance with a necessary function of the IP. In these methods, a development of an IP circuit is made to confirm an evaluation, and design data thereof is registered previously in a computer. Then, when a request for utilization of the IP is made by the customer, the foregoing registered data is directly down-loaded on the corner of a chip of the embedded array LSI or the standard cell LSI, and a mask is designed. In this case, since the design of the arrangement of the IP is individually made in accordance with a necessary function, the function required is satisfied. However, a size and an arrangement of each transistor that is a constituent component, and wirings among the transistors are peculiar to the IP.
Accordingly, when the IP is used in the embedded array and the standard cell, all of the masks necessary for the LSI formation are necessary for each circuit demanded by the customer.
Any, jump in price of a photomasks because of microfabrication of a new semiconductor process is also potential problem. IF the wiring width is large in the photomask of the old process, then the IP cannot be formed, resulting in a jump in development cost of each product. A method to control the development cost is thorough using FPGA (Field Programmable Gate Array) is effective. However, since the FPGA loads a memory, the FPGA generally has a lower speed and a lower integration degree. An FPGA shows a processing speed lower by a several fraction of that of the gate array and requires a chip area several times as wide as that of the gate array. The FPGA has much difficulty to cope with the increase in the development cost than the gate array. Under such circumstances, it is desired to realize an ASIC circuit capable of loading low cost, high speed and high performance IPs.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a semiconductor integrated circuit having a lower wiring region and an upper wring region on a semiconductor substrate, said semiconductor integrated circuit comprising: the semiconductor substrate; a gate array region formed on the semiconductor substrate described above; an IP (Intellectual Property) region constituted by a plurality of semiconductor devices formed on the semiconductor substrate, the IP region having a predetermined function; a first wiring layer formed in the lower layer wiring region on the semiconductor substrate; a second wiring layer formed in the IP region; and a third wiring layer formed in the upper wiring region of the gate array region, wherein the third wiring layer is wider than the first and second wiring layers.
According to other aspect of the present invention, in a method of forming a semiconductor integrated circuit, said method of making semiconductor integrated device comprising: a step for forming a plurality of semiconductor devices respectively in first and second regions of a semiconductor substrate; a step for forming a gate array portion in the first region by forming a plurality of first wirings respectively connected to the plurality of semiconductor devices formed in the first region and for forming at least one IP (Intellectual Property) region having a predetermined function in the second region by forming a plurality of second wirings connecting the plurality of semiconductor devices to each other formed in the second region; and a step for forming a plurality of third wirings connecting the plurality of first wirings to each other, and the plurality of first wirings and the plurality of second wirings.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5915025 (1999-06-01), Taguchi et al.
patent: 6054872 (2000-04-01), Fudanuki et al.
patent: 6304100 (2001-10-01), Kobayashi
Kaneko Yoshio
Tamura Yoshihisa
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