Semiconductor circuit device capable of accurately testing...

Details Semiconductor circuit device capable of accurately testing... Semiconductor circuit device capable of accurately testing...

2003-03-07

2004-10-19

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189050, C365S189060, C365S189110, C365S202000

Reexamination Certificate

active

06807116

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly to a semiconductor circuit device referred to as a system LSI having memory and logic integrated on the same semiconductor substrate. More particularly, the present invention relates to the configuration of externally testing an embedded memory with respect to signal/data timing conditions.
2. Description of the Background Art
A DRAM-embedded system LSI having a DRAM (Dynamic Random Access Memory) and a logic device or microprocessor integrated on the same semiconductor substrate is becoming wide-spread. The DRAM-embedded system LSI has the following advantages, different from a conventional system in which a discrete DRAM and a discrete logic device or microprocessor are mounted on a printed board with soldering or the like.
(1) Since there are no limitations by pin terminals, the width of a data bus between a DRAM and a logic device can be widened, data transfer rate can be improved, and, accordingly, system performance can be improved.
(2) A data bus between the DRAM and a logic device is formed of on-chip interconnection lines smaller in load than on-board wires. Consequently, an operation current at the time of data transfer can be decreased and data can be transferred at high speed.
(3) Since a system is formed in a single package, external data bus wiring and external control signal wiring are unnecessary, the occupation area of the system on a printed board can be reduced, and the overall system can be down-sized.
FIG. 8
is a diagram schematically showing an example of the configuration of a conventional DRAM-embedded system LSI. In
FIG. 8
, a DRAM-embedded system LSI
500
includes: a logic
502
for performing a predetermined operational process; a DRAM macro
504
for storing at least data required by logic
502
; and a logic external bus
508
for connecting logic
502
to an external device via a pad group
518
.
Logic
502
may be a logic device dedicated to perform the predetermined operational process, or may be a microprocessor. Logic
502
is merely required to perform a process using data stored in DRAM macro
504
.
DRAM macro
504
includes: a DRAM core
510
for storing data; a test interface circuit (TIC)
512
for allowing an external direct access to DRAM core
510
to perform a test; and a selecting circuit
517
for selecting one of an internal logic bus
506
of logic
502
and an internal test bus
516
from test interface circuit
512
and coupling the selected one to an internal memory bus
515
in accordance with a test mode instruction signal MTEST. Internal memory bus
515
is connected to DRAM core
510
. Test interface circuit
512
is coupled to pad group
518
via an external test bus
514
.
Each of buses
506
,
508
,
514
,
515
and
516
includes signal lines for transmitting a control signal, an address signal and data. Since the internal logic bus
506
, internal memory bus
515
, and internal test bus
516
do not suffer from limitation due to the count of pin terminals, the bus widths can be made sufficiently wide.
Read data from DRAM core
510
is transferred directly to test interface circuit
512
and logic
502
, with selecting circuit
517
bypassed. However, in
FIG. 8
, to simplify the drawing, a transfer path of internal read data is not shown.
FIG. 8
shows both logic external bus
508
and external test bus
514
being coupled to pad group
518
. Alternatively, external test bus
514
and logic external bus
508
may be selectively connected to common pads in accordance with test mode instruction signal (MTEST). In accordance with test mode instruction signal MTEST, selecting circuit
517
couples test interface circuit
512
to DRAM core
510
.
FIG. 9
is a diagram showing the signals for DRAM core
510
in a list form. In
FIG. 9
, to DRAM core
510
, a clock signal CLK is supplied as an operation timing determination signal. DRAM core
510
takes in signals/data and outputs data, synchronously with clock signal CLK.
DRAM core
510
receives, as operation control signals, a dock enable signal CKE for setting validity/invalidity of an internal clock signal in DRAM core
510
, a row activating signal /ACT for activating an internal row selecting operation, a row inactivating signal /PRE for driving a selected row to a not-selected state, an auto refresh instruction signal /REFA for instructing refresh of memory cell data in DRAM core
510
, a read operation instruction signal /RE for instructing reading of data, and a write operation instruction signal /WR for instructing data writing operation.
For designating an address of a memory cell, DRAM core
510
is further supplied with a 13-bit row address signal RA<12:0>, a 4-bit column address signal CA<3:0>, a spare row space addressing address signal RAsp for designating a spare memory cell row, and a spare column space addressing address signal CAsp for designating a spare column.
Spare row space addressing address signal RAsp and spare column space addressing address signal CAsp are used to access a spare memory cell of DRAM core
510
and determine whether the spare memory cell is defective or not in a test performed before a defect address fuse programming.
When spare space addressing address signals RAsp and CAsp are at the H level, a spare memory cell space is designated. When they are at the L level, a normal memory cell space is designated.
To DRAM core
510
is further supplied with data D<127:0> of 128 bits and spare write data SD<1:0> of two bits. From DRAM core
510
, read data Q<127:0> of 128 bits and spare read data SQ<1:0> of two bits are outputted. When an address of the spare memory cell space is designated, a spare memory cell for redundancy replacement is designated. Therefore, by designating a spare memory cell by spare space addressing address signals RAsp and CAsp and writing/reading data to/from the designated spare memory cell, the spare memory cell can be tested directly from the outside of the DRAM core.
As shown in
FIG. 9
, DRAM core
510
has a larger number of input/output signals, as compared with a general discrete DRAM. Test interface circuit
512
generates the signals and data as shown in
FIG. 9
for DRAM core
510
in a testing operation in accordance with signals applied from an external tester.
If test interface circuit
512
transmits/receives the signals/data shown in
FIG. 9
to/from the external tester by external test bus
514
via pad group
518
, the number of lines of the signals/data becomes larger than the number of pins of the external tester, so that a test cannot be performed. Even if a test can be performed, due to the large number of signal lines and data lines necessary for a device to be test, the number of devices which can be measured at the same time decreases, and the test cost increases.
Test interface circuit
512
is provided to reduce the number of pins required in the test and to allow a direct access to DRAM core
510
from the outside of the device to improve testability of DRAM core
510
.
FIG. 10
is a diagram showing, in a list form, external signals for test interface circuit
512
. The signals shown in
FIG. 10
are transferred between an external tester and test interface circuit
512
via external test bus
514
shown in FIG.
8
.
In
FIG. 10
, a test clock signal TCLK and a test clock enable signal TCKE are applied to test interface circuit
512
. Test clock signal TCLK and test clock enable signal TCKE are used in a test operation mode in place of clock signal CLK and clock enable signal CKE applied to DRAM core
510
in the normal operation mode.
To test interface circuit
512
, further, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write operation instruction signal /WE are applied. In accordance with a combination of logic levels, for example, at the rising edge of the test clock signal, of these control signals /CS, /RAS, /CAS and /WE, an operation mode of the DRAM

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