Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-15
2006-08-15
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S013000
Reexamination Certificate
active
07093215
ABSTRACT:
An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.
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Nakata Kazuhisa
Ootani Katsuhiro
Sahara Yasuyuki
Sekido Shinsaku
Garbowski Leigh M.
Matsushita Electric - Industrial Co., Ltd.
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