Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-12-27
2001-10-30
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S774000, C257S750000, C257S665000
Reexamination Certificate
active
06310396
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a monolithically integrated semiconductor circuit apparatus having a semiconductor substrate, in which or on which a plurality of circuit elements are formed. The circuit elements are electrically interconnected and, if necessary, connected to contact points, in particular to contact points disposed at an edge of the semiconductor substrate. The electrical interconnection is done with interconnect patterns which are provided in a plurality of contact-making planes, beginning with a first contact-making plane, which is closest to the main surface of the semiconductor substrate, and ranging to a last contact-making plane. The invention furthermore relates to a method for fabricating such a monolithically integrated semiconductor circuit apparatus.
Fuse structures are used in integrated circuits in order to interrupt (“fuse”) or reestablish (“antifuse”) electrically conductive connections through the use of laser irradiation after the actual production process. In programmable logic arrays (PLAs), the logic combinations are programmed by fuses. In safety-critical circuits, fuses are used to prevent access to test modes of the circuit by unauthorized persons. In the case of the use of fuses as in the method and the device of the invention, the fuses are used in order to activate redundant circuit sections, namely memory cells, and to disconnect defective ones. When using polysilicon fuses or else metal fuses for the redundancy activation of defective memory cells in dynamic random access memories (DRAMs) with many metalization layers, problems arise with regard to the reliability of the activation by burning through or “blowing” polysilicon interconnects or metal interconnects (M
1
interconnects). These problems are further intensified, and have remained unsolved heretofore, when a semiconductor memory device normally having two metalization layers (M
1
, M
2
) and a digital logic component having, by contrast, at least one further metalization plane (M
3
) are intended to be combined on one and the same semiconductor substrate. Since the logic component thus has more than two metalization layers, severing polysilicon interconnects located at a deeper level for the purpose of activating the fuse is associated with great risks and faults.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a monolithically integrated semiconductor circuit apparatus and a method for fabricating such a monolithically integrated semiconductor circuit apparatus which overcome the above-mentioned disadvantages of the heretofore-known methods and devices of this general type and in which a risk-free and fault-free activation of fuses can be ensured even when there are more than two metalization planes.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a monolithically integrated semiconductor circuit apparatus, the method including the steps of forming circuit elements on or in a semiconductor substrate, the circuit elements including at least one complete semiconductor memory device with associated drive circuits and a complete digital logic component monolithically integrated on the semiconductor substrate; forming interconnect patterns in a plurality of contact-making planes, the plurality of contact-making planes including a first contact-making plane, a penultimate contact-making plane, and a last contact-making plane, the first contact-making plane being closer to a main surface of the semiconductor substrate than the penultimate contact-making plane, and the penultimate contact-making plane being closer to the main surface of the semiconductor substrate than the last contact-making plane; electrically interconnecting the circuit elements with the interconnect patterns; forming a protection device from one of the interconnect patterns in at least a partial region of the penultimate contact-making plane, the protection device having at least one of fuses and antifuses; and assigning the protection device to a redundancy activation of at least one of defective memory cells and memory cell groups of the semiconductor memory device.
In accordance with another mode of the invention, contact points are formed at an edge of the semiconductor substrate; and the contact points and the circuit elements are electrically interconnected.
In accordance with yet another mode of the invention, the at least one complete semiconductor memory device is a dynamic read-write memory or DRAM having a storage capacity of at least 1 megabit and preferably at least 4 megabits.
In accordance with yet a further mode of the invention, a first interconnect pattern including polysilicon is formed in the first contact-making plane, a second interconnect pattern including a metal is formed in a second contact-making plane, and a third interconnect pattern including a metal is formed in a third contact-making plane.
In accordance with an added mode of the invention, further interconnect patterns including a metal are formed in further contact-making planes.
With the objects of the invention in view there is also provided, a monolithically integrated semiconductor circuit apparatus, including a semiconductor substrate having a main surface; a plurality of circuit elements disposed on or in the semiconductor substrate, the plurality of circuit elements including at least one completely formed semiconductor memory device having at least one of memory cells and memory cell groups, drive circuits associated with the at least one completely formed semiconductor memory device, and a complete digital logic component monolithically integrated on the semiconductor substrate; a plurality of contact-making planes including a first contact-making plane having a first interconnect pattern, a penultimate contact-making plane having a penultimate interconnect pattern with a partial region, and a last contact-making plane having a last interconnect pattern, the first contact-making plane being closer to the main surface of the semiconductor substrate than the penultimate contact-making plane, the penultimate contact-making plane being closer to the main surface of the semiconductor substrate than the last contact-making plane, the first, the penultimate, and the interconnect patterns being provided for electrically interconnecting the plurality of circuit elements; and a protection device formed at least in the partial region of the penultimate interconnect pattern, the protection device including at least one of a fuse and an antifuse and being assigned to a redundancy activation for defective ones of the memory cells and memory cell groups in the semiconductor memory device. A fuse is defined as any connection that may be severed or interrupted, an antifuse is defined as any interruption in a connection that may be connected.
In accordance with another feature of the invention, contact points or contact pads are disposed on the semiconductor substrate. At least one of the first, penultimate, and last interconnect patterns electrically interconnect at least one of the plurality of circuit elements to the contact points.
In accordance with yet another feature of the invention, the semiconductor substrate includes an edge, and the contact points are disposed at the edge of the semiconductor substrate.
In accordance with a further feature of the invention, the at least one complete semiconductor memory device is a dynamic read-write memory or a DRAM having a storage capacity of at least 4 megabytes, and preferably at least 16 megabytes.
In accordance with yet a further feature of the invention, the fuse or the antifuse is formed of a metal.
In accordance with another feature of the invention, the plurality of contact-making planes includes at least the first contact-making plane having the first interconnect pattern formed of polysilicon, and a second and a third contact-making plane having a second and a third interconnect pattern formed of a metal.
In accordance with yet
Clark Jhihan B
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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