Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-18
2003-11-04
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000
Reexamination Certificate
active
06642745
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC §119 to Japanese Patent Application No. 2001-119509 filed on Apr. 18, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a semiconductor circuit to which a Silicon On Insulator (SOI) technique is applied. Particularly, the invention pertains to a predischarge method of a dynamic circuit including n-channel transistors connected in series.
2. Description of Related Art
A typical example of a dynamic circuit including n-channel transistors connected in series is shown in FIG.
1
. In
FIG. 1
, the dynamic circuit is implemented by an inverter Q
103
as an output driver, p-channel transistors Q
101
and Q
102
which are connected with an input side of the inverter Q
103
, and a logic circuit section configured by connecting n-channel transistors Q
104
, Q
105
, Q
106
and Q
107
are connected in series. The p-channel transistor Q
101
functions as a precharge circuit for precharging a dynamic node D
10
. The p-channel transistor Q
102
is a leaker for maintaining the electric potential of the dynamic node D
10
. Gates of the n-channel transistors Q
105
, Q
106
and Q
107
are connected respectively to input terminals
51
,
52
and
53
, and an output of the inverter Q
103
is connected to an output terminal
54
. Moreover, a clock signal CLK is input into a gate of the p-channel transistor Q
101
and a gate of the n-channel transistor Q
104
.
When the clock signal CLK to be input into the gate of the p-channel transistor Q
101
is at a low level, the p-channel transistor Q
101
is turned ON and the precharge circuit is actuated. As a result, the input side (dynamic node D
10
) of the inverter Q
103
is precharged to a high level, an output side of the inverter Q
103
is pulled down to a low level. The p-channel transistor Q
102
is turned ON.
Nodes
0
,
2
and
4
are pulled down to a low level, and nodes
1
and
3
can be possibly pulled up to a high level depending on the operating state before precharge.
When the Clock signal CLK becomes a high level, an evaluation period begins, in this state, the node
4
is pulled up to a high level and the n-channel transistor Q
107
is turned ON, and when the node
3
is changed to a low level, an electric current flows from the node
1
to the node
3
due to bipolar action. Similarly, an electric current flows from a node between the n-channel transistors Q
104
and Q
105
to the node
1
, as a result, noise is mixed into an electric potential of the dynamic node D
10
. Since this electric current is supplied from the precharge circuit side, an electric potential of the input side of the inverter Q
103
becomes unstable, and noise is mixed into the output of the inverter Q
103
. This causes malfunction of circuits in later stages.
Therefore, in order to prevent malfunction, a p-channel transistor Q
108
for predischarge actuated by a clock signal CLK is connected to an intermediate node, in this example to the node
1
as shown in FIG.
2
. As a result, during precharge in a state where the clock signal CLK is at a low level, the p-channel transistor Q
108
is turned ON, so that the node
1
is pulled down to a low level. With such a configuration, even if the node
3
is changed to a low level, since the node
1
was already at a low level at this time, the electric current does not flow from the node
1
to the node
3
.
However, in the configuration shown in
FIG. 2
, when the p-channel transistor Q
108
is added to each intermediate node, wiring should be connected to each intermediate node, so that a layout area increases. Moreover, in a case where the configuration of the logic circuit section implemented by connecting n-channel transistors in series becomes complicated, a lot of p-channel transistors for predischarge need to be connected to the intermediate nodes, so that circuit dimensions become large.
SUMMARY OF THE INVENTION
A semiconductor circuit according to an embodiment of the present invention includes: a first stage block including a plurality of first stage dynamic circuits and configured to output a predischarged result of the respective first stage dynamic circuits to blocks cascade connected to later stages, each of the first stage dynamic circuit includes predischarge elements connected respectively to dynamic nodes of the respective first stage dynamic circuits to predischarge the dynamic nodes, configured such that the dynamic nodes of the respective first stage dynamic circuits are precharged with a predetermined cycle; a predischarge signal generating circuit configured to generate a predischarge signal to actuate the respective predischarge elements before precharge timing of the respective dynamic nodes of the respective first stage dynamic circuits; and at least more than one next stage blocks including a plurality of next stage dynamic circuits and configured to output predischarge results of the respective next stage dynamic circuits sequentially to blocks cascade connected to later stages, each of the next stage dynamic circuit configured to input the predischarge result of the previous block so as to predischarge dynamic nodes of the respective next stage dynamic circuits, configured such that the dynamic nodes of the respective next stage dynamic circuits are precharged with a predetermined cycle.
In addition, a semiconductor circuit according to another embodiment of the present invention includes: a first stage block including a plurality of first stage dynamic circuits and configured to output a predischarge result in the respective first stage dynamic circuits to blocks cascade connected to later stages, each of the first stage dynamic circuit configured to input predischarge data so as to predischarge dynamic nodes of the respective first stage dynamic circuits, configured such that the dynamic nodes of the respective first stage dynamic circuits are precharged with a predetermined cycle and; a predischarge data input circuit configured to generate the predischarge data and to input the predischarge data into the first stage block; a predischarge signal generating circuit configured to generate a predischarge signal to actuate the predischarge data input circuit before precharge timing of the respective dynamic nodes of the respective first stage dynamic circuits; and at least more than one next stage blocks including a plurality of next stage dynamic circuits and configured to output predischarge results of the respective next stage dynamic circuits sequentially to blocks cascade connected to later stages, each of the next stage dynamic circuit configured to input the predischarge result of the previous block so as to predischarge dynamic nodes of the respective next stage dynamic circuits, configured such that the dynamic nodes of the respective next stage dynamic circuits are precharged with a predetermined cycle.
Further, a semiconductor circuit according to another embodiment of the present invention includes: a first stage block including a plurality of first stage dynamic circuits, each of the first stage dynamic circuit includes predischarge elements connected respectively to dynamic nodes of the respective first stage dynamic circuits to predischarge the dynamic nodes, configured such that the dynamic nodes of the respective first stage dynamic circuits are precharged with a predetermined cycle; at least more than one next stage blocks including a plurality of next stage dynamic circuits, each of the next stage dynamic circuit includes predischarge elements connected respectively to dynamic nodes of the respective next stage dynamic circuits to predischarge the dynamic nodes, configured such that the dynamic nodes of the respective next stage dynamic circuits are precharged with a predetermined cycle; and a predischarge signal generating circuit configured to generate a predischarge signal to actuate the respective predischarge elements of the respective first stage dynamic circuit
Kabushiki Kaisha Toshiba
Tan Vibol
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